Nonvolatile memory array wordline driver circuit with voltage tr

Details Nonvolatile memory array wordline driver circuit with voltage tr Nonvolatile memory array wordline driver circuit with voltage tr

1993-01-22

1994-02-15

Gossage, Glenn

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518909, 365226, 365185, 307449, 307452, 307264, G11C 1606, G11C 514

Patent

active

052875369

ABSTRACT:
A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed.

REFERENCES:
patent: 4368524 (1983-01-01), Nakamura et al.
patent: 4583205 (1986-04-01), Watanabe
patent: 4642798 (1987-02-01), Rao
patent: 4677590 (1987-06-01), Arakawa
patent: 4820941 (1989-04-01), Dolby et al.
patent: 4823318 (1989-04-01), D'Arrigo et al.
patent: 4864591 (1989-09-01), Marquot

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