Nonvolatile memory array organization and usage

Details Nonvolatile memory array organization and usage Nonvolatile memory array organization and usage

2007-03-13

2007-03-13

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S185130, C365S185110, C365S230030

Reexamination Certificate

active

11124221

ABSTRACT:
A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.

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