Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-12-01
2000-10-24
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
36518522, G11C 1604
Patent
active
061377171
ABSTRACT:
A writing circuit for a nonvolatile memory has eight circuit units for bit parallel processing. Each circuit unit has 16 first D flip-flops for address 0 to address F, and one second D flip-flop. The eight circuit units hold in their own 16 first D flip-flops write data of 8 bits fed in bit parallel fashion with respect to each of the 16 addresses. The totally eight second D flip-flops simultaneously hold 8 bits of verify data read from memory cells in bit parallel fashion. In verify operation, in each of the eight circuit units, the write data held in the first D flip-flops are given 16 address attributes, respectively, and compared with the verify data held by the second D flip-flop in an address sequence of the 16 address attributes to make sure of coincidence between the data.
REFERENCES:
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 5377145 (1994-12-01), Kynett et al.
patent: 5784315 (1998-07-01), Itoh
Nelms David
Sharp Kabushiki Kaisha
Yoha Connie C.
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