Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-12
2003-05-20
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185130, C365S185170
Reexamination Certificate
active
06567315
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique that can be effectively adapted to a write control system in an electrically erasable and programmable non-volatile memory and more specifically to a technique that can be effectively adapted to a flash memory being capable of simultaneously erasing data, for example, in a predetermined unit.
A flash memory uses, as a memory cell, a non-volatile memory element consisting of a MOSFET of the double-gate structure including a control gate and a floating gate. The write system in the flash memory has been sorted to a system utilizing the FN tunnel phenomenon and a hot-electron system. In the system utilizing the FN tunnel phenomenon, a voltage is applied across the control gate and substrate (or well region) or across the control gate and source or drain and a threshold voltage is changed through implantation or release of charges to and from the floating gate by utilizing the FN tunnel phenomenon.
Meanwhile, in the system utilizing the hot-electron, a threshold voltage is changed through implantation into the floating gate of hot electrons generated in the channel by applying a current across the source and drain under the condition that a high voltage is impressed to the control gate. In the case of the hot-electron system, the charges are generally extracted from the floating gate in the FN tunnel. Moreover, a flash memory is often structured so that data is erased, even when any write system is employed, in unit of memory cell (sector) connected to only one word line or in unit of a plurality of sectors (blocks) using in common the well region and source lines.
SUMMARY OF THE INVENTION
FIGS.
16
(A) and
16
(B) show an example of voltage applied to a memory cell in the write system utilizing the FN tunnel (system for raising a threshold voltage of the memory cell by write operation). FIG.
16
(A) shows voltage applied to a memory cell for selection, namely for write operation, while FIG.
16
(B) shows voltage applied to a memory cell for no-selection, namely for no-write operation. As shown in FIGS.
16
(A) and
16
(B), the voltage of 0V is applied to the source and drain of the selected memory cell, while the write rejection voltage of 5V is applied to the source and drain of the non-selected memory cell.
A flash memory may be sorted to a memory array called the NAND type memory in which memory elements Qm are connected in series as shown in FIG.
17
(A) and a memory array called the AND type memory in which memory elements Qm are connected in parallel as shown in FIG.
17
(B).
Of the flash memories explained above, the AND type memory array is often structured, as shown in FIG.
17
(B) in the manner that the local bit line LBL to which the drains of the memory elements Qm are connected is connected to the main bit line GBL via the selected MOSFET Qs. In such a memory array, when the write system as shown in
FIG. 16
is employed, if a write rejection voltage of 5V is applied to the memory element Qm via the main bit line and local bit line depending on the write data, the more the memory capacity of memory array increases, the longer the bit line becomes and the more the number of bit lines increases. Accordingly, there arises a problem that a load capacitance of bit line becomes larger, the time required until the bit line reaches the predetermined potential becomes larger, and thereby the time required for write operation also becomes longer and power consumption also becomes high.
Moreover, in the memory array wherein the write rejection voltage is generated within an internal power supply circuit such as a voltage-boosting circuit, if a load capacitance of bit line increases, the power supply capability of the internal power supply circuit must be intensified. Therefore, the occupation area of circuit becomes larger and thereby a chip size is also increased. Moreover, when the write system by the FN tunnel is employed, there exists a problem that the scale-down of memory element becomes difficult and integration degree cannot be improved because an element isolation region must be provided among the cells for insulation between memory cells and the dielectric strength of elements forming a memory cell must be further raised in comparison with the hot-electron system.
It is therefore an object of the present invention to provide a non-volatile memory such as a flash memory that can reduce the total write operation time.
It is another object of the present invention to provide a non-volatile memory such as a flash memory that can reduce the power consumption.
It is further object of the present invention to provide a non-volatile memory that can improve the integration degree of a memory array.
The aforementioned and the other objects and novel features of the present invention will become more apparent from the description of the present invention and the accompanying drawings.
The summary of the present invention disclosed in this specification will be explained below.
Namely, in the write method of a non-volatile memory including a memory array comprising a plurality of word lines and bit lines and a plurality of memory cell lines, a plurality of memory cells connected to any one of word lines are connected in parallel in each memory cell line, and connecting a first common connection node of each memory cell line to the bit lines via first switch means and a second common connection node of the memory cell lines to a common voltage supply line via second switch means, after the first common connection node of the memory cell lines is charged via the second switch means with a first voltage for write operation, at the time of write operation, from the common voltage supply line in the opposite direction to the bit lines, a second voltage lower than the first voltage is selectively applied to the bit lines depending on the write data and a current is applied to the memory cells to be selected while the charged first voltage is discharged by controlling the first and second switch means, and after a current is not applied to the non-selected memory cells that are not the write operation object, the write operation is conducted selectively to the memory cells by applying the third voltage for write operation to any lines among the word lines.
In more detail, in the non-volatile memory including the so-called AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, a switch MOSFET which can short-circuit between the local bit line and local drain line is provided to precharge the local bit line and local drain line by supplying a write rejection voltage from the side of common drain line (opposite side of the main bit line). Thereafter, the charges used for precharge of the local bit line connected to the selected memory cells for the write operation are pulled toward the main bit line by selectively making conductive the selected MOSFET through application of 0V or the voltage smaller than the write rejection voltage to the main bit line depending on the write data and also application of the voltage, similar to the application voltage to the main bit line, to the gate of the selected MOSFET between the local bit line and main bit line. Subsequently, electrons are implanted to the floating gate with the FN tunnel in the selected memory cells to which the data is written by applying the write voltage to the word lines.
According to the means explained above, the precharge up to the write rejection voltage is required for the write operation only to the local bit lines and local drain lines having comparatively lower parasitic capacitance. In this case, since it is enough for the main bit line to raise the voltage thereof up to the voltage lower than the write rejection voltage, the time required for precharge of the main bit line can be reduced to improve the write operation speed and the load capacitance of the internal power supply circuit during the write operation can be reduced to remarkably lower the power consumption
Kanamitsu Michitaro
Kubono Shoji
Kurata Hideaki
Nozoe Atsushi
Takase Yoshinori
Mai Son
Miles & Stockbridge P.C.
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