Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2003-03-05
2004-07-27
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185230, C365S185120, C365S185110, C365S185330, C365S185290
Reexamination Certificate
active
06768671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly to nonvolatile memory and method of operation thereof to control erase disturb.
2. Description of the Related Art
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. A variety of different types of nonvolatile semiconductor memory devices are known, include types based on the storage of charge in discrete trapping centers of a dielectric layer of the structure, and types based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. A common type of stored charge device is the stacked gate transistor, also known as a floating gate transistor, in which cell programming typically is achieved using an electron transport mechanism such as Fowler-Nordheim (“FN”) tunneling, channel hot-electron (“CHE”) injection, or channel-initiated secondary electron injection (“CISEI”) as disclosed in, for example, U.S. Pat. No. 5,659,504 issued Aug. 19, 1997 (Bude et al., “Method and Apparatus for Hot Carrier Injection”).
Self-aligned double-polysilicon stacked gate structures have been used in a variety of array architectures, including NAND and NOR architectures and various contactless virtual ground configurations. Examples of virtual ground array architectures and nonvolatile semiconductor memory devices include those disclosed in the following publications: U.S. Pat. No. 6,175,519 issued Jan. 16, 2001 to Liu et al.; U.S. Pat. No. 5,959,892 issued Sep. 28, 1999 to Lin et al.; U.S. Pat. No. 5,646,886 issued Jul. 8, 1997 to Brahmbhatt; U.S. Pat. No. 5,418,741, issued May 23, 1995 to Gill, U.S. Pat. No. 5,060,195 issued Oct. 22, 1991 to Gill et al., and Ohi et al., “An Asymmetrical Offset Source/Drain Structure for Virtual Ground Array Flash Memory with DINOR Operation,” Symposium on VLSI Technology, Digest of Technical Papers, May 17-19, 1993, pp. 57-58.
In many array architectures, cells are erased into a high threshold voltage state in groups such as a block or sector (page) using FN tunneling. Unfortunately, in block erase and page erase operations, data cells in the unselected rows are exposed to bias conditions that progressively raise, or disturb, their threshold voltage. These bias conditions can, over a great many such erase cycles, cause data in the memory array to become corrupted. This problem is known as erase disturb.
FIG. 1
is a simplified schematic diagram showing a layout diagram of a typical memory
100
in which isolation structures are used to manage erase disturb. Isolation structures are used to create a number of isolated p-wells
101
,
103
,
105
and
107
(in practice, many more such swells would be created). Isolation is achieved in the
FIG. 1
example by placing the p-wells (such as
101
,
103
,
105
and
107
) into n-wells (such as
102
,
104
,
106
and
108
), which are spaced apart throughout the memory
100
. Oxides and other dielectrics may also be used. Having a limited number of blocks within each p-well and isolating the p-wells from one another is an effective technique for reducing this type of erase disturb. Unfortunately, the use of such isolation structures increases the size of the array of memory cells.
BRIEF SUMMARY OF THE INVENTION
What is needed is an erase technique that does not depend on the use of isolation structures to reduce the type of erase disturb that occurs when a large number of blocks are placed within the same bulk region.
We have developed an erase technique that uses peripheral circuitry instead of isolation structures within the array of memory cells to reduce the type of erase disturb that occurs when a large number of blocks are placed within the same bulk region.
This and other advantages are realized individually or collectively in various embodiments of the present invention. One embodiment of the present invention is a nonvolatile semiconductor memory array integrated circuit comprising an array of nonvolatile memory cells generally organized in a plurality of pages, each page being accessible by a word line and the bits therein being accessible by bit lines; an address input; and an X-decoder having an input coupled to the address input and an output coupled to the word lines of the nonvolatile memory cell array. The output of the X-decoder logically sections the memory cell array into a plurality of groups of blocks of pages, and the X-decoder being responsive to an address on the address input during erase mode for selecting one of the groups and one of the blocks within the selected group and for applying a first voltage to at least one page of the selected block in the selected group for erasing the memory cells thereof, a second voltage to the pages of the selected group other than the selected at least one page to avoid erasing the memory cells thereof, and a third voltage to the pages of the groups other than the selected group to avoid disturb of the memory cells thereof.
Another embodiment of the present invention is a nonvolatile semiconductor memory array integrated circuit comprising an array of nonvolatile memory cells generally organized in a plurality of blocks having a plurality of pages, each block being selectable by a block select line and each page being selectable by a word line; a plurality of X-decoder group circuits, each having a plurality of block select outputs and word line outputs coupled to a group of the block select lines and word lines of the memory cell array; a plurality of voltage switches respectively coupled to the X-decoder group circuits by respective first and second voltage outputs; and a pre-decoder having an X-address input, global group select outputs, global block select outputs, and global page select outputs. The X-decoder group circuits are respectively coupled to the global group select outputs of the pre-decoder, and each of the X-decoder group circuits is coupled to the global block select outputs of the pre-decoder. The voltage switches are respectively coupled to the global group select outputs of the pre-decoder for furnishing a large positive potential on the first voltage output and a ground potential on the second voltage output for a selected group, and for furnishing a ground potential on the first voltage output and a large negative potential on the second voltage output for an unselected group.
Another embodiment of the present invention is a method for operating a nonvolatile semiconductor memory array integrated circuit in a block erase mode, the memory array having an array of nonvolatile memory cells generally organized in a plurality of pages, with each page being accessible by a word line and the bits therein being accessible by bit lines. The method comprises logically sectioning the memory cell array into a plurality of groups of blocks of pages; selecting one of the groups and one of the blocks within the selected group in accordance with a portion of an X memory address; applying a first voltage on the pages in the selected block of the selected group for erasing the memory cells thereof; applying a second voltage on the pages in unselected blocks of the selected group to avoid erasing the memory cells thereof; and applying a third voltage on the pages in the groups other than the selected group to avoid disturb of the memory cells thereof.
Another embodiment of the present invention is a method for operating a nonvolatile semiconductor memory array integrated circuit in a page erase mode, the memory array having an array of nonvolatile memory cells generally organized in a plurality of pages, with each page being accessible by a word line and the bits therein being accessible by bit lines. The method comprises logically sectioning the memory cell array into a plurality of groups of blocks of pages; selecting one of the groups and one of the blocks within the selected group in accordance with a first portion of an X memory
Kim Kwang-ho
Lee Poongyeub
Park Eungjoon
Park Joo Weon
Altera Law Group LLC
NexFlash Technologies, Inc.
Tran Andrew Q.
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