Nonvolatile floating gate semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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357 235, G11C 1140

Patent

active

048706159

ABSTRACT:
A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

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patent: 4462090 (1984-07-01), Iizuka
patent: 4558344 (1985-12-01), Perlegos
patent: 4710900 (1987-12-01), Higuchi
patent: 4725983 (1988-02-01), Terada
patent: 4752912 (1988-06-01), Guterman

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