Nonrecursive digital filter

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G06F 1531

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048414638

ABSTRACT:
The signal path of a nonrecursive digital filter contains a series combination of like delay elements each providing a delay equal to the period of a clock signal or to a multiple thereof, each of the delay elements having a subtracter and a read-only memory associated therewith. The minuend inputs of each of the subtracters associated with the first half of delay elements is connected to the input of the associated delay element, and that of each of the substracters associated with the second half of delay elements to the output of the associated delay element, while the subtrahend inputs of all subtracters are connected to the center tap of the series combination of delay elements and to the first input of an adder. The output of each of the subtracters is coupled to the address input of the associated read-only memory, which has its output connected to one of the inputs of a multiple-input adder. The output of the latter is fed to the second input of the adder. Each read-only memory contains the function e=bd, where d is the output signal of the subtracter, and b is a value dependent on the difference between the center-tap signal value and the input-signal value of the respective delay element of the first half of delay elements or the output-signal value of the respective delay element of the second half. This digital filter shows adaptive behavior.

REFERENCES:
patent: 3824384 (1974-07-01), Murata et al.
patent: 3892953 (1975-07-01), Nussbaumer
patent: 4571719 (1976-02-01), Cadquist et al.
patent: 4701874 (1987-10-01), Akai et al.
patent: 4949206 (1976-04-01), Edwards et al.
Patent Abstracts of Japan, vol. 9, No. 131 (E-319)-(1854) Jun. 6, 1985, Nippon Denshin Denwa Kosha.
Internation Journal of Electronis, vol. 55, No. 4, Oct. 1983, pp. 675-679; On the Use of Look-Up Tables in the Microprocessor Implementation of Digital Filters-A. N. Skodras.

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