Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Reexamination Certificate
2002-11-05
2003-11-04
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
C428S210000, C428S195100, C427S503000, C427S504000, C427S510000, C427S515000
Reexamination Certificate
active
06641899
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the production of patterns on a substrate having regions with different compositions or different surface treatment. More particularly, it relates to a method of producing fine patterns on substrates used in, for example, the microelectronics industry on which electronic devices are fabricated. It is also related to devices fabricated in accordance with the methods. The patterns are fabricated accurately and inexpensively without the use of lithography. The present invention also provides many additional advantages, which shall become apparent as described below.
BACKGROUND OF THE INVENTION
A number of applications and technologies involve structures having a well-defined arrangement of chemically distinct components at the surface of a substrate. A common example is a substrate surface having metal conductor regions separated by insulator regions. Normally, these structures are defined by patterning processes such as lithography, embossing, and stamping, and have length scales ranging from 10nanometers to several microns. In many of these systems it may be necessary or highly beneficial to apply an additional component or treatment to only one of the components at the surface. One technique for performing this task is through the use of a mask to protect regions where this additional application or treatment is not desired. Effectively, the mask material directs this treatment to the intended surfaces that are fully exposed. Unfortunately, typical procedures to generate a mask by lithographic or other means can be expensive and error prone. Thus, a method in which these conventional approaches can be circumvented would be highly advantageous.
A particular example in which such strategies would be useful involves integrated circuits comprised of metal and dielectric components. It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area is increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the dielectric materials existing between metal lines and/or to minimize the thickness of layers having comparatively larger dielectric constants, e.g., cap barrier layers. Both of these approaches reduce the effective dielectric constant, k
eff
, of the components between metal lines, and as a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays. Unfortunately, these strategies are difficult to implement due to limitations in maintaining significant properties, i.e., mechanical, barrier, electrical, etc., that result with a reduction in thickness or change in the chemistry of the layers.
SUMMARY OF THE INVENTION
This invention relates to a method to fabricate mask layers onto a pre-patterned substrate having two or more chemically distinct surface regions. The mask layer is deposited by a selective reaction approach that provides self-alignment of the layers. This method can apply to any technology or application involving a chemically or physically heterogeneous substrate including: interconnect structures for high speed microprocessors, application specific integrated circuits (ASICs), flexible organic semiconductor chips, and memory storage. Other structures that can be fabricated utilizing this method include: displays, circuit boards, chip carriers, microelectromechanical systems (MEMS), chips for hi-thoughput screening, microfabricated fluidic devices, etc. The utility of this method stems from a simple and robust means in which the replication of a patterned substrate to generate a mask layer can be performed, circumventing the requirement for expensive and error prone methods, such as lithography. Thus, the present invention provides an extremely advantageous alternative to the prior art techniques.
In the example of integrated circuits, the effective dielectric constant is reduced by the use of a process wherein layers are selectively placed upon the metal lines. To do this, mask layers are first applied to the dielectric or hard mask surfaces. In accordance with the invention, these layers are generated by mechanisms involving selective chemical reactions as described below. The layers can be self-aligned such that lithographic processes are not required to define the features. Upon self-alignment on the dielectric/hardmask surfaces, these layers, can then be used as a mask for subsequent deposition of other layers which serve as diffusion barriers to copper, oxygen and/or water, layers which reduce the electromigration attributes of the metal lines, and seed layers.
Thus, in the example of integrated circuits, the use of the self-aligned masks allows a simplified fabrication process in which the effective dielectric constant between metal lines can be reduced through selective application of various materials to the metal lines. This is central to maximizing the propagation speed of interconnect signals and ultimately provides faster overall circuit performance. Furthermore, this invention leads to a higher level of protection and reliability of interconnect structures as the errors attributed to conventional patterning methods are eliminated and to reduced processing costs. Although the utilization of the self-aligned masks is described for integrated circuits, this method is useful for any application wherein the modification of a specific component in a pre-patterned substrate is beneficial.
Thus, the invention is directed to a process wherein a mask is applied to a pre-patterned substrate, through selective chemical reactions described below, that replicates the underlining pattern. This mask can then be utilized for treatment or material deposition onto specific components of the pre-patterned substrate. The use of the self-aligned masks allows a unique process in which masks can be generated without the need to perform additional pattern defining steps.
Another application of this invention is its use for semiconductor packaging substrates which are comprised of conductors (usually copper) and insulators (usually epoxy, polyimide, alumina, cordierite glass ceramic and the like) disposed adjacent to each other. Commonly, the conductors must be protected from external ambients and processing exposures such as soldering and wet etching. This protection can be achieved by using the various methods of forming selective coatings on the conductor. Alternately, selective coating on the dielectric by one of the exemplary methods can leave the metal exposed for further processing by methods such as electroless plating to add additional metal layers such as nickel, cobalt, palladium, gold and others on top, without exposing the dielectrics to these process steps. The ability to accomplish these selective modifications without the use of lithographic processing leads to cost reductions and is particularly advantageous in microelectronic packaging, which is very cost sensitive.
Although the utilization of the self-aligned masks is described for microelectronic parts, this method is useful for any application whereby the modification of a specific component in a pre-patterned substrate is beneficial.
Thus, this invention is directed to a method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of the masking material to the substrate; and allowing at least a portion of the masking material to preferentially attach to portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first regions may comprise copper and may be patterned electrical interconnects.
According to the present inventi
Colburn Matthew E
Gates Stephen M
Hedrick Jeffrey C
Huang Elbert
Nitta Satyanarayana V
Lam Cathy
Morris Daniel P.
Ohlandt Greeley Ruggiero & Perle L.L.P.
LandOfFree
Nonlithographic method to produce masks by selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonlithographic method to produce masks by selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonlithographic method to produce masks by selective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3160056