Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2000-04-18
2002-03-12
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S344000
Reexamination Certificate
active
06356136
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a nonlinear resistor circuit using capacitively-coupled multi-input MOSFETS, and more particularly to a nonlinear negative resistor circuit using capacitively-coupled multi-input MOSFETs.
BACKGROUND ART
Devices and circuits having a nonlinear current-voltage (I-V) characteristic, especially those having a negative resistance characteristic, play important roles in logic circuits, memory circuits, oscillators, impedance conversion circuits, various nonlinear signal processing circuits, and chaos generators.
There have been proposed various types of such devices, including a device circuit having a &Lgr;-type I-V characteristic and realized through combined use of bipolar junction transistors (BJTs) and/or field effect transistors (FETs) (First reference: L. O. Hill, D. O. Pederson, and R. S. Pepper, “Synthesis of Electronic Bistable Circuits,” IEEE Transactions on Circuit Theory, vol. CT-10, pp. 25-35, 1963).
Further, a method of effectively realizing the circuit through employment of a technique for integrating two junction FETs (J-FETs) has been proposed (Second reference: G. Kano and H. Iwasa, “A new A-type Negative Resistance Device of Integrated Complementary FET Structure,” IEEE Transactions. Electron Devices, vol. 21, no. 7, pp. 448-449, 1974).
Moreover, a &Lgr;-type transistor circuit that realizes a &Lgr;-type negative resistance characteristic by use of two MOSFETs has been proposed and applied to an impedance conversion circuit and a neuron circuit (Third reference: Kennosuke Sugisaki, Hisahiro Sekine, Yoshifumi Sekine, Kohei Nakamura, and Masatoshi Suyama, “A &Lgr;-type transistor using two MOS-FETs,” Proc. Denki-Kankei-Gakkai, Tohoku-shibu Rengo-Taikai, 2G9, p. 270, 1978; Fourth reference: Hisahiro Sekine, Kennosuke Sugisaki, Hitoshi Sato, Yoshifumi Sekine, and Masatoshi Suyama, “The equivalent inductance using a &Lgr;-type transistor,” IEICE Trans., vol. J63-C, no. 5, pp. 325-327, 1980; and Fifth reference: Hoshifumi Sekine, Masahiko Nakamura, Toshiyuki Ochiai, and Masatoshi Suyama, “Utilization of a &Lgr;-type transistor for a hardware neuron model,” IEICE Trans., vol. J68-A, no. 7, pp. 672-679, 1985).
DISCLOSURE OF THE INVENTION
The above-described conventional circuit cannot be integrated by a standard CMOS process in which only enhancement-type MOSFETs are available, because at least one of the MOSFETs in the circuit must be of a depletion type,
An object of the present invention is to provide a nonlinear resistor circuit which utilizes capacitively-coupled multi-input MOSFETs in order to enable integration thereof by a standard CMOS process, and which can realize two types of nonlinear resistance characteristics; i.e., &Lgr;-type and V-type nonlinear resistance characteristics. Thus, the present invention solves the above-described problems.
The capacitively-coupled multi-input MOSFET comprises a MOSFET and a plurality of capacitors which are connected to the gate terminal in parallel and provide a number of input terminals. The operation of the capacitively-coupled multi-input MOSFET can be controlled through control of voltage applied to one or more of the capacitively-coupled input terminals. The structure of the circuit is the same as a multi-input floating gate MOSFET, which effects a linear weighted summation of input, such as a VMOSFET (see Sixth reference; T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring Gate-level Weighted Sum and Threshold Operations,” IEEE Transactions. Electron Devices, vol. 39, no. 6, pp. 1444-1455, 1992) and an MFMOSFET (see Seventh reference: H. R. Mehrvarz and C. Y. Kwok, “A Novel Multi-Input Floating-Gate MOS Four-Quadrant Analog Multiplier,” IEEE J. of Solid State Circuits, vol. 31, no. 8, pp. 1123-1131, 1996).
Since such linear summation does not play an important role in the nonlinear resistor circuit of the present invention, the input coupling capacitors are not required to have linear characteristics. Therefore, as used herein, the term “capacitively-coupled multi-input MOSFET” refers to a more general circuit configuration, including a VMOSFET. Therefore, the nonlinear resistor circuit according to the present invention can be integrated by a less-expensive CMOS process in which linear capacitors are not available.
Further, the size of the nonlinear resistor circuit according to the present invention can be reduced if a floating gate device such as a VMOSFET can be used.
In order to achieve the above object, the present invention provides:
[1] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs, comprising a core circuit which has a nonlinear resistance characteristic and which comprises an enhancement-type first-channel MOSFET having a capacitively-coupled multi-input gate terminal, and an enhancement-type second-channel MOSFET having a capacitively-coupled multi-input gate terminal, the source terminals of the MOSFETs being connected with each other.
[2] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [1] above, wherein the first channel of the core circuit is an N channel, and the second channel of the core circuit is a P channel, so that a &Lgr;-type current-voltage characteristic is obtained.
[3] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [2] above, wherein the &Lgr;-type current-voltage characteristic is varied through application of an external control voltage.
[4] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [3] above, wherein, as shown in FIGS.
6
(
a
)-
6
(
p
), a fifth potential (v
X
) is provided between the drain terminal (A) of the N-channel MOSFET and a first input/output terminal (X); a sixth potential (V
Y
) is provided between the drain terminal (B) of the P-channel MOSFET and a second input/output terminal (Y); a first potential (v
P1A
, v
P1X
) is provided between the drain terminal (A) of the N-channel MOSFET and a first capacitor (C
P1
) connected to the gate of the P-channel MOSFET or between the first input/output terminal (X) and the first capacitor (C
P1
); a second potential (V
P2B
, V
P2Y
) is provided between the drain terminal (B) of the P-channel MOSFET and a second capacitor (C
P2
) connected to the gate of the P-channel MOSFET or between the second input/output terminal (Y) and the second capacitor (C
P2
); a third potential (v
N1B
, v
N1Y
) is provided between the drain terminal (B) of the P-channel MOSFET and a third capacitor (C
N1
) connected to the gate of the N-channel MOSFET or between the second input/output terminal (Y) and the third capacitor (C
N1
); and a fourth potential (v
N2B
, v
N2Y
) is provided between the drain terminal (B) of the P-channel MOSFET and a fourth capacitor (C
N2
) connected to the gate of the N-channel MOSFET or between the second input/output terminal (Y) and the fourth capacitor (C
N2
).
[5] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [1] above, wherein the first channel of the core circuit is a P channel, and the second channel of the core circuit is an N channel, so that a V-type current-voltage characteristic is obtained.
[6] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [5] above, wherein the V-type current-voltage characteristic is varied through application of an external control voltage,
[7] A nonlinear resistor circuit using capacitively-coupled multi-input MOSFETs as described in [6] above, wherein, as shown in FIGS.
8
(
a
)-
8
(
p
), an eleventh potential (v
X
) is provided between the drain terminal (B) of the P-channel MOSFET and a first input/output terminal (X); a twelfth potential (v
Y
) is provided between the drain terminal (A) of the N-channel MOSFET and a second input/output terminal (Y); a seventh potential (v
N2A
, v
N2X
) is provided between the drain terminal (B) of the P-channel MOSFE
Aihara Kazuyuki
Horio Yoshihiko
Watarai Kenichi
Cunningham Terry D.
Dinh Paul
Japan Science and Technology Corporation
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