Noninverting Bi-CMOS gates with propagation delays of a single B

Details Noninverting Bi-CMOS gates with propagation delays of a single B Noninverting Bi-CMOS gates with propagation delays of a single B

1992-01-22

1993-09-07

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 1902

Patent

active

052432378

ABSTRACT:
In a noninverting Bi-CMOS gate, one or more passgates are utilized in the control path leading to a bipolar output transistor which switches the output of the Bi-CMOS gate. The control gate of one of the MOS transistors of a passgate is connected to an input signal of the Bi-CMOS gate. The control gate of the other MOS transistor is connected to the complement of the input signal. The output of the passgate is connected to the base of the bipolar output transistor. More than one such passgate connected to an input signal and its complement can be used. If multiple passgates are used, the outputs of the passgates may be tied together. This technique, utilizing the switching of the passgates with the input signals and their complements, is employed to create a family of Bi-CMOS noninverting gates such as buffers and AND gates. The propagation delay through the noninverting Bi-CMOS gates of the present invention are roughly equal to the propagation delay of a single Bi-CMOS inverter.

REFERENCES:
patent: 4633220 (1986-12-01), Burgess
patent: 4703203 (1987-10-01), Gallup et al.
patent: 4890017 (1989-12-01), Masuda et al.
patent: 4948994 (1990-08-01), Akioka et al.
patent: 5107142 (1992-04-01), Bhamidipaty
patent: 5148052 (1992-09-01), Yellamilli

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