Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-02-07
2004-08-10
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S537000, C702S084000, C700S110000
Reexamination Certificate
active
06774647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to methods and systems for inspecting or testing CMOS circuits. More specifically, the invention relates to measuring the density of local switching activity in CMOS integrated circuits and perturbations of the electrical behavior of devices in such circuits due to the presence of temporally coincident local switching activity.
2. Prior Art
Modern integrated circuits may have an extremely large number and extremely high density of gates. The large number and high density of gates causes problems that can be very difficult to diagnose or assess. For example, assume we have a planar integrated circuit which has M of its gates within some area X. Each of these gates when it switches, draws S coulombs. The power lines supplying Vdd to this area can provide a maximum of A amps during a short time interval of Y. If during the course of running a set of instructions, N of the M gates switch over a time interval of Y, then the total charge required to support this activity is NS. If the required charge NS is greater than the local charge AY that can be supplied to the area X over the time Y, then the local voltage will be reduced. The magnitude of the decrease will depend on the details of the power bus system. Such decreases in local power supply voltage can produce errors in the operation of an integrated circuit (IC) since thresholds can be missed, and switching times slowed.
Such a failure cannot be detected by looking just at individual devices since the failure arises from the interaction of many normally functioning devices. An ideal solution would be able to detect the presence of simultaneous electrical activity in areas of the chip on the time scale of the time constant of the power supply system. That solution would then be able to deduce changes in the local supply voltage during this activity.
High densities of circuit operation in small areas and over short periods of time can also produce local heating effects, which introduce errors into the operation of the circuit. High densities of switching activity also increase the possibility of cross talk and errors associated with this. This can trigger false switching activity, which even when it does not produce errors in the operation of the chip, should be avoided, and a technique that allows the identification of cross-talk effects will be valuable.
Given that ICs meant for mobile applications generally have stringent limits on their power dissipation, if an IC consumes more power than its design predicts, it is important to know where and when power is being dissipated in a chip, even when there is no heating or loading of the power supply generating errors in computation.
It is also important to be able to identify particular instructions that consume anomalous amounts of power in a chip, and to determine both where in a chip such anomalous powers are being dissipated, and when during the execution of the instruction set by a chip this is occurring, especially if design criteria are being exceeded. Finally, leakage effects are becoming major contributors to power consumption in modern chips. Various circuit techniques, such as multiple threshold CMOS, are used to control the leakage in ICs and a tool to verify the effectiveness of such techniques would be valuable.
CMOS technology is nominally a low power technology since in the absence of switching activity, there is little or no power dissipation. However, switching activity generates power losses in a chip. The power dissipation attributable to a change of output state per gate under normal circumstances is proportional to the frequency of switching, the load on the gate, and the square of the bias voltage, Vdd. As the density of gates and operating frequencies increase in ICs, total power dissipation per unit area increases also, even though by the scaling relationships which are the starting point for decreasing device sizes, there are also decreases in the individual gate loads and bias voltages. The automatic process by which device layouts are produced on chips can result in situations where the density of switching activity in a limited region of the chip and over a short period of time in the operation of the chip may exceed basic limits of power delivery and extraction for the design.
Modern CMOS integrated circuits can contain over 50,000,000 active devices/cm
2
. Present and future microprocessors dissipate power at the tens to hundreds of watts level. Such high levels of power and power density can cause significant problems in operation, reliability etc. This is especially so if the power dissipation is localized in small regions of a chip and for short intervals of time during the execution of instruction sets. Current device densities are high enough, and the power dissipation per device during electrical switching is large enough, that switching activity by many devices in a small area can decrease the power supply voltage in that area or raise the local temperature.
These perturbations are usually time dependent effects, depending on the device layout, and the time dependence of the switching by the neighboring gates. Such local loading of the power supply or heating can produce errors in the operation of devices in this local area at particular periods of time. Errors which occur only due to particular instructions or sets of instructions, and only during particular instances of time in executing a group of instructions, can be difficult to identify by traditional techniques and methods.
A method for the determination of the behavior of any given device in a chip, in the presence of electrical activity by neighboring gates and devices, is needed now. The complexity of the design process, the use of automated methods of circuit placement, and the size of modern programs must leave the identification of such “hot spots” to the qualification process for the chip. The effects of these “hot spots” can be removed through changes in chip layouts, decoupling of the power supply lines etc., which are applied when such a problem can be identified.
Present techniques for solving these problems include modeling and simulations of chips. Unfortunately, the complexity of the chips, and the instruction sets is such that capabilities are far short of needs at present. The computational times required for detailed simulations prevent large scale applications of such techniques. The modeling and simulations are too long and also rely on assumptions about the fabrication and physical properties of the chip which may not correspond to real chips.
Physical methods for identifying such problems include gross measurements of IC supply currents on the assumption that high currents are associated with high levels of switching activity. Aside from problems associated with leakage currents complicating the analysis, such approaches produce no local information in the absence of additional test circuitry on the chip. On-chip control circuits can be used to isolate or limit circuit switching so that currents associated with specific circuits, or test patterns, can be identified. This extra circuitry adds complexity to the chip, and also extra cost. High impedence probes can either be built into the chip, or placed with tools such as focused ion beam milling to measure local circuit activity. Diodes can be built into circuits to measure local temperatures. All of these techniques add complexity to the design and fabrication of the chip, require costly space, and can slow performance.
The devices in a modern integrated circuit can be spread over areas of over 4 cm
2
. Given that the devices can number over 50M, it is impossible to examine each one individually, and in many cases, there is a tremendous premium on being able to look at the full chip in a single measurement. In such situations, the inability to spatially resolve each individual gate is irrelevant if there are unique signatures for the activity by groups of gates. Of special interest is to efficiently identify regions of anomalous
Kash Jeffrey Alan
Knebel Daniel R.
Tsang James Chen-Hsiang
Ludwin Richard M.
Patel Paresh
Scully Scott Murphy & Presser
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