Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1978-06-27
1980-01-29
James, Andrew J.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
357 22, 357 65, 357 71, 29589, 29590, 427 82, 427 91, H01L 2980, H01L 2348, H01L 2946
Patent
active
041864107
ABSTRACT:
A nonalloyed ohmic contact (110-112, 120-122) to an n-type Group III(a)-V(a) compound semiconductor body (102-104) is formed by epitaxially growing a Group III(a)-V(a) n.sup.++ -layer (106-108, 106'-108') doped to at least 10.sup.19 cm.sup.-3 between the semiconductor body and a metal contact layer (110-112). The metal layer forms an ohmic contact without requiring heating above the eutectic temperature. In order to avoid contamination of the metal-semiconductor interface, a metal contact layer (120-122) may be deposited in situ after MBE growth of the n.sup.++ -layer. This technique results in both a metal-semiconductor interface with smoother morphology and also an ohmic contact without heating above the eutectic temperature. These procedures are specifically described with reference to the fabrication of GaAs FETs.
REFERENCES:
patent: 3242391 (1966-03-01), Gorman
patent: 3490140 (1970-01-01), Knight et al.
patent: 3684930 (1974-01-01), Collins et al.
patent: 3711745 (1973-01-01), Moroney
patent: 3855613 (1974-12-01), Napoli et al.
patent: 3898353 (1975-08-01), Napoli et al.
patent: 3914785 (1975-10-01), Ketchow
patent: 4011583 (1977-03-01), Levinstein
Cho Alfred Y.
Di Lorenzo James V.
Niehaus William C.
Bell Telephone Laboratories Incorporated
James Andrew J.
Urbano Michael J.
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