Nonaligned access to random access memory

Details Nonaligned access to random access memory Nonaligned access to random access memory

2005-12-13

2005-12-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S231000

Reexamination Certificate

active

06975553

ABSTRACT:
Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.

REFERENCES:
patent: 6070003 (2000-05-01), Gove et al.
patent: 6507534 (2003-01-01), Balluchi

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