Non-volatile semiconductor storage system

Details Non-volatile semiconductor storage system Non-volatile semiconductor storage system

2011-01-18

2011-01-18

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185090, C365S185240

Reexamination Certificate

active

07872910

ABSTRACT:
In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

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