Non-volatile semiconductor storage device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185120

Reexamination Certificate

active

07808835

ABSTRACT:
In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

REFERENCES:
patent: 5886937 (1999-03-01), Jang
patent: 6147912 (2000-11-01), Kitazawa
patent: 6473327 (2002-10-01), Ishizuka
patent: 6980472 (2005-12-01), Ditewig et al.
patent: 2005512268 (2005-04-01), None
patent: 03050813 (2003-06-01), None

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