Non-volatile semiconductor memory with SCRAM hold cycle prior to

Details Non-volatile semiconductor memory with SCRAM hold cycle prior to Non-volatile semiconductor memory with SCRAM hold cycle prior to

1989-04-05

1990-10-23

Tarcza, Thomas H.

Cryptography

Electric signal modification

Having production of printed copy

380 3, 380 4, 380 49, 365229, 307 64, 371 14, H04L 900, G11B 2328

Patent

active

049658280

ABSTRACT:
A non-volatile memory system includes an SRAM and a backup store of E.sup.2 PROMs. In the event of a short duration power interruption, the memory system enters a hold mode in which data maintenance power is supplied to the SRAM by discharging a backup capacitor, and accessing of the SRAM by a host computer is halted. If the backup capacitor voltage does not fall below a threshold before power is restored, the hold mode is terminated and accessing by the host computer continues. If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM by further discharging of the backup capacitor. Row parity and column parity information are accumulated by a bit-per-chip accumulation technique that allows convenient error correction on a "per chip" basis. Data is encrypted and decrypted on the basis of a fully erasable magnetic key.

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