Non-volatile semiconductor memory using split bit lines

Details Non-volatile semiconductor memory using split bit lines Non-volatile semiconductor memory using split bit lines

1999-02-25

2001-02-13

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130, C365S063000

Reexamination Certificate

active

06188605

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory using memory transistors each having a floating gate and a control gate.
2. Description of the Related Art
In an electrically erasable programmable ROM (EEPROM: Electrically Erasable Programmable ROM) with memory cells each composed of a single transistor, each memory cell is constructed of a transistor in a double gate structure having a floating gate and a control gate. In the case of such a transistor in a double gate structure, write of information is effected in such a manner that hot electrons injected from a drain region of the floating gate are accelerated toward a source region and passed through a gate insulating film so as to be injected into the floating gate. Read of the information is effected in such a manner that a difference in the operation of the memory transistors is detected according to whether or not charges have not been injected in the floating gate.
Such a memory structure can be roughly classified into two kinds of a “stack gate type” and a “split gate type”. The memory cell in the split gate type is structured as shown in
FIG. 5
in such a fashion that on a channel formed between a drain region
1
and source region
2
, a floating gate
4
is partially superposed over the source region
2
through an insulating film
3
whereas a control gate
5
is superposed over the floating gate through an insulating film
6
.
The drain region
1
serves a common region with an adjacent memory cell, and is connected to a bit line
8
through a contact hole
7
. The source region also serves as a common region with the adjacent memory cell.
FIG. 6
shows the schematic structure of a non-volatile semiconductor memory using such split gate type memory cells. In a memory cell array
11
with a plurality of memory cells
10
arranged in a matrix with n rows and m columns, each memory cell
10
is located at each of crossing points of n word lines WL (
0
-n-1) and m bit lines BL (
0
-m-1). The control gate
5
of the memory cell
10
in
FIG. 5
is connected to the word line WL, and the drain (region)
1
in
FIG. 5
is connected to the bit line BL. The source
2
in
FIG. 4
of the memory cell
10
in each row connected to adjacent word lines WL is connected to a common source line SL (
0
-n/2-1). For example, the memory cell connected both word lines WL
0
and WL
1
is connected to the common source line SL
0
. A row address decoder
12
selects one of the word lines WLs on the basis of an applied load address data RAD and also supplies a voltage to the selected word line WL according to each of signals ES, PG and RE indicative of an erase mode, program mode and read mode, respectively. The row address decoder
12
supplies a voltage according to each mode to the common source line SL relative to the selected word line W. A column address decoder
13
selects one of the bit lines BLs on the basis of an applied column address data CAD, and applies a voltage, which is controlled by a write/read control circuit
14
, to the bit line BL selected in accordance with a program mode PG and a read mode signal RE.
On the other hand, in order to prevent discharge of the bit line in the erase and read modes and erroneous write in the program mode, between each bit line BL and a potential line ARGND, an MOS transistor
15
is arranged which is controlled by each of the inverted signals *Y
0
to *Ym-
1
of the decode outputs from the column address decoder
13
. For example, if the bit line BL
0
is selected as a result that the column address data CAD has been decoded in the read mode and program mode, the decode output *Y
0
is at a “L” level and the other decode outputs *Y
1
to *Ym-
1
are at an “H” level. Thus, the other bit lines BL
1
to BLm-
1
than the selected bit line BL
0
are connected to the potential line ARGND through the MOS transistors
15
which have turned “ON”.
Referring to
FIGS. 5 and 6
, an explanation will be given of the erase mode, program mode and read mode of the non-volatile semiconductor memory.
(1) Erase Mode
When the erase mode signal ES becomes active, the row address decoder
12
applies an erase voltage Ve (e.g. 14.5 V) to the word line (e.g. WL
0
) selected on the basis of the address data RAD, and applies a ground potential (0 V) to the other non-selected word lines WL
1
to WL. The row address decoder
12
also applies the ground potential to all the common source lines SL
0
-SLn/
2
-
1
.
On the other hand, the column address decoder
13
places all the decode inverted outputs *Y
0
-*Ym-
1
at the “H” level so that the all the MOS transistors
15
are “ON”. Thus, all the bit lines BLs are connected to the potential line ARGND. At this time, since the potential line ARGND is at a grounding potential, all the bit lines BLs are in a state where the grounding potential is applied to them. Thus, an erase voltage of 14.5 V is applied to the control gates
5
of all the memory cells connected to the word line WL
0
, and a voltage of 0 V is applied to the drains
1
and source
2
thereof. In the memory cell
10
, in which the capacitive coupling between the sources
2
and floating gate
4
is much larger than that between the control gate
5
and floating gate
4
, the potential of the floating gate
4
is fixed to the same 0 V as the source
2
by the capacitive coupling, and the potential difference of 14.5 V is created between the control gate
5
and floating gate
4
. Thus, the F-N (Fowler-Nordheim) tunnel current flows through a tunneling oxide film (
6
a
in FIG.
4
). Namely, the electrons which have been injected into the floating gate are extracted from the protruding portion of the floating gate
4
into the control gate
5
. Accordingly, the batch erase of the memory cells connected to the one word line W
1
can be implemented.
(2) Program Mode (Write Mode)
When the program mode signal PG becomes active, the row address decoder
12
applies a select voltage Vgp (e.g. 2 V) to the word line (e.g. WL
0
) selected on the basis of an applied row address data RAD, and applies a grounding potential of 0 V to the other non-selected word lines WL
1
-WLn-
1
. The row address decoder
12
supplies a program voltage Vp (e.g. 12.2 V) to the common source line SL
0
relative to the selected word line WL
0
. On the other hand, the column address decoder
13
connects the bit line BL (e.g. BL
0
) selected on the basis of the column address data CAD to a read/write circuit
14
. Therefore, the voltage based on the write data applied to an input/output terminal I/O is applied to the selected bit line BL
0
. For example, if “0” is applied to the input/output terminal I/O, a write enable source voltage Vse (0.9 V) is applied to the bit line BL
0
. If “1” is applied to the input/output terminal I/O, a write disable source voltage Vsd (4.0 V) is applied to the bit line BL
0
. The other non-selected bit lines BL
1
to BLm-
1
are connected to the potential line ARGND set at the write disable source voltage Vsd (4.0 V).
Thus, in the memory cell
10
specified by the word line WL
0
and bit line BL
0
, when the input/output terminal I/O is “0”, 12.2 V is applied to the source
2
, 0.9 V is applied to the drain
1
and 2.0 V is applied to the control gate
5
. As a result, although carries flow from the drain
1
to the source
2
, the potential at the floating gate
4
is approximately equal to that at the source
2
because of the capacitive coupling therebetween. Therefore, the carries are injected as hot electrons into the floating gate
4
through the insulating film
3
. On the other hand, in the non-selected memory cells
10
, since the voltages at the drain
1
, source
2
and control gate
5
do not satisfy the programming condition, injection of the carries into the floating gate
4
does not occur.
(3) Read Mode
When the read mode signal RE is active, the row address decoder
12
applies a selecting voltage Vgr (4.0 V) to the word line WL (e.g. WL
0
) selected on the basis of a row address data RAD, and also applies a groundin

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