Non-volatile semiconductor memory structure

Details Non-volatile semiconductor memory structure Non-volatile semiconductor memory structure

2002-03-13

2004-08-03

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S314000, C257S621000, C257S928000

Reexamination Certificate

active

06770950

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a non-volatile semiconductor memory cell structure and method of manufacture. More particularly, the present invention relates to a flash memory cell structure and method of manufacture.
2. Description of Related Art
Non-volatile memory is used inside various electronic components for holding structural data, programming data or repeatedly accessed data. Non-volatile programmable memory such as electrically erasable programmable read-only-memory (EEPROM) is now routinely used inside personal computers and electronic equipment. A conventional EEPROM employs a floating gate transistor structure to write data into or erase data from a memory cell. However, erasure speed of this type of memory cell is relatively slow. Memory having a fast erasure speed, commonly referred to as flash memory, has now become a mainstream product in the market. In general, flash memory can be roughly divided into two major types, namely, NAND type and NOR type. In the NAND type flash memory, memory cells are connected in series by connecting a drain terminal of a previous memory cell with a source terminal of a following serial-connected memory cell. That is, the drain terminal of each of the NAND type memory cells is commonly using a same region of the source terminal of the following serial-connected memory cell. In the NOR type flash memory, a source region is commonly used by NOR type memory cells, for example 6. That is, the source terminals of the NOR type memory cells are connected to each other by the commonly used source region.
FIGS. 1
to
3
are cross-sectional views showing the steps for producing a conventional non-volatile semiconductor memory cell. First, as shown in
FIG. 1
, a substrate
100
is provided. A deep P-well layer
102
, an N-well layer
104
and a channel-doped region
106
are formed over the substrate
100
. The channel-doped region
106
is a p-doped region near the surface of the substrate
100
. The N-well layer
104
is beneath the channel-doped region
106
and the deep P-well layer
102
is beneath the N-well layer
104
.
As shown in
FIG. 2
, a stack gate
108
is formed over the channel-doped region
106
. The stack gate
108
comprises of a first dielectric layer
108
a
, a floating gate
108
b
, a second dielectric layer
108
c
and a control gate
108
d.
After the fabrication of the stack gate
108
, ion implantation and heat drive-in processes are carried out to form a P-well
114
, a source terminal
112
and a drain terminal
110
as shown in FIG.
3
. The source terminal
112
and the drain terminal
110
are heavily N-doped (n
+
) regions. The distribution of the source terminals localizes the channel-doped regions
106
into separate blocks such that each pair of stack gates
108
in a block uses a common drain terminal
110
. The P-well
114
is under the drain terminal
110
. Due to the heat drive-in process, the P-well
114
expands into regions under the stack gate
108
and overlaps with a portion of the channel-doped region
106
.
In a conventional method of manufacturing non-volatile semiconductor memory cell, the distribution of dopants inside the channel-doped/P-well overlapping region underneath the stack gate is often laterally non-uniform. The variation in dopant concentration inside the channel-doped/P-well overlapping region will lead to threshold voltage deviation of memory cells.
In addition, the spread of the P-well region is often subjected to the effect caused by the thermal budget. If the P-well regions expand further towards the source terminals due to drive-in, the blocks normally localized by the source terminals may be too close or conduct leading to reliability problem for the memory cells.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a non-volatile semiconductor memory cell structure and method of manufacture capable of improving the uniformity of dopant distribution inside a region underneath a stack gate structure of the memory cell.
A second object of this invention is to provide a non-volatile semiconductor memory cell structure and method of manufacture capable of improving the reliability of the memory cell.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a non-volatile semiconductor memory cell structure. The memory cell structure is built over a substrate. The substrate comprises of, from top to bottom, a shallow first-type well layer, a second-type well layer and a deep first-type well layer. A multiple-layered stack gate is over the substrate. The substrate further contains a multiple of source terminals and drain terminals. The source terminal and the drain terminal together form an adjacent pair. Each of the source terminal and the drain terminal is formed between a pair of stack gates. The source terminal has a depth great enough to pass through the shallow first-type well layer and connect with the second-type well layer. The drain terminal is close to the surface of the shallow first-type well layer. Both the source terminal and the drain terminal are second-type doped.
This invention also provides a method of fabricating a non-volatile semiconductor memory cell. The method includes the following steps. A deep first-type well layer, a second-type well layer and a shallow first-type well layer are sequentially formed over a substrate. A stack gate is formed over the shallow first-type doped well layer. A source terminal and a drain terminal is formed such that the source terminal passes through the shallow first-type well layer and connects with the second-type well layer and the drain terminal is formed close to the surface of the first-type well layer. Both the source terminal and the drain terminal are second-type doped.
In this invention, if the shallow first-type well layer and the deep first-type well layer are both P-doped layers, the second-type well layer, the source terminal and the drain terminal are N-doped layers. Conversely, if the shallow first-type well layer and the deep first-type well layer are both N-doped layers, the second-type well layer, the source terminal and the drain terminal are P-doped layers.
The stack gate of this invention may comprise of a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer. The second dielectric layer, for example, is a three-layered oxide
itride/oxide (ONO) structure.
Alternatively, the stack gate of this invention may comprise of a first dielectric layer, a trap layer, a second dielectric layer and a control gate layer. The first dielectric layer and the second dielectric layer can be oxide layers and the trap layer can be a silicon nitride layer. In other words, a three-layered oxide
itride/oxide (ONO) structure is formed underneath the control gate.
The source terminal within the substrate comprises of a lightly doped section and a heavily doped section. The lightly doped section is close to the surface of the substrate while the heavily doped section is underneath the lightly doped section in connection with lightly doped section. Furthermore, the heavily doped section passes through the shallow first-type well layer and connects with the second-type well layer.
The source terminal that passes through the shallow first-type well layer is formed, for example, by performing a one-time ion implantation. By controlling implant depth of the ions, a lower dopant concentration is established near the surface of the substrate while a higher dopant concentration is established close to the junction between the second-type well layer and the shallow first-type well layer.
Alternatively, the source terminal that passes through the shallow first-type well layer is formed, for example, by performing more than one ion implantation. A first ion implantation is performed to form a lightly doped region near the surface of the substrate. A second ion implantation is performed to form a heavil

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