Non-volatile semiconductor memory having a memory cell array div

Details Non-volatile semiconductor memory having a memory cell array div Non-volatile semiconductor memory having a memory cell array div

1996-11-22

1998-06-30

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518502, 36518509, 36518516, 36518529, G11C 1134

Patent

active

057743983

ABSTRACT:
Digit lines 31 to 34 and word lines 35 to 38 are provided. NMOS transistors 1 to 4 serving as Y selectors, a memory cell divided into two memory cell groups 25 and 26, a write circuit 21, a sense amplifier 22, a Y decoder 23, an X decoder 24, and a selector for selecting the memory cell groups 25 and 26 are provided in correspondence to the digit and word lines. The selector includes a PMOS transistor 27 and NMOS transistors 28 to 30. The memory cell group 25 is selected when a most significant address bit signal 101 is inputted as "0" level signal, and the memory cell group 26 is selected when the signal 101 is inputted as "1" level signal.

REFERENCES:
patent: 5426611 (1995-06-01), Maruyama
patent: 5521867 (1996-05-01), Chen et al.
patent: 5526309 (1996-06-01), Jinbo
patent: 5592415 (1997-01-01), Kato et al.
patent: 5594689 (1997-01-01), Kato
patent: 5621689 (1997-04-01), Sakakibara et al.
patent: 5621690 (1997-04-01), Jungroth et al.

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