Non-volatile semiconductor memory device with writing...

Details Non-volatile semiconductor memory device with writing... Non-volatile semiconductor memory device with writing...

2001-11-06

2002-11-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Data security

C365S189011, C365S185190

Reexamination Certificate

active

06487115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more particularly to a non-volatile semiconductor memory device that performs data writing for a prescribed unit area at a time.
2. Description of the Background Art
In recent years, a flash memory has come into use as a file storage medium, and storage capacity thereof has been increased. As a way of increasing the storage capacity, a technique for writing data of at least two bits in one cell has been widely discussed.
FIG. 10
is a schematic diagram showing a structure of a memory cell MC in a flash memory.
Referring to
FIG. 10
, the memory cell MC of the flash memory includes a source
22
and a drain
23
that are n
+
regions formed on a p type substrate
21
. Memory cell MC further includes a floating gate
24
and a control gate
25
. Floating gate
24
and control gate
25
are stacked one on the other on p type substrate
21
, insulated from each other by an insulating film
26
. In particular, the insulating film between floating gate
24
and control gate
25
is also called an inter-poly insulating film
26
a,
and the insulating film between floating gate
24
and p type substrate
21
is also called a tunnel insulating film
26
b.
Accordingly, memory cell MC corresponds to an n channel field effect transistor formed on p type substrate
21
.
Control gate
25
is coupled to a word line WL for selecting the memory cell MC. Source
22
and drain
23
are coupled to a source line SL and a bit line BL, respectively.
In memory cell MC of a data erased state as an initial state, an electron
27
is drawn out of floating gate
24
.
Specifically, assume that a negative high voltage Vnn and a ground voltage GSS are applied to control gate
25
and source
22
, respectively, of memory cell MC. In this case, in the memory cell MC, electron
27
is drawn from floating gate
24
by Fowler-Nordheim tunneling, so that data is erased.
Data writing to memory cell MC is carried out by injection of electron
27
into floating gate
24
by the Fowler-Nordheim tunneling.
Specifically, under a condition where source line SL is open, a high voltage Vpp and ground voltage GSS are applied to control gate
25
and drain
23
via word line WL and bit line BL, respectively. This causes the Fowler-Nordheim tunneling, so that electron
27
is injected to floating gate
24
, and thus, data is written therein. If high voltage Vpp and a write inhibit voltage Vdi are applied to control gate
25
and drain
23
, respectively, then the data writing is not effected.
Here, the threshold voltage Vth of memory cell MC in the data written state with electron
27
having been injected to floating gate
24
becomes higher than that in the data erased state.
Therefore, when data is written into memory cell MC in the data erased state, the stored data can be read out according to the level of threshold voltage Vth of the memory cell MC. For the data reading, bit line BL is precharged in advance, which is discharged for a prescribed period of time by applying a constant voltage to word line WL coupled to control gate
25
, and then, the resulting potential of bit line BL is detected.
Specifically, at the time of data reading, bit line BL is precharged in advance to a prescribed voltage Vdr. Source line SL is provided with ground voltage GSS. A prescribed voltage Vwr for data reading is applied to selected word line WL for a prescribed period of time. Control gate
25
of corresponding memory cell MC is thus set to prescribed voltage Vwr.
When these voltages Vwr and Vdr are properly set taking into account the threshold voltage Vth of memory cell MC with data written therein, memory cell MC would not turn on if data writing has been completed therefor, so that it maintains the precharged charges. On the contrary, memory cell MC would turn on if the data writing has not been completed yet, in which case the precharged charges are discharged via memory cell MC to source line SL, so that the potential of bit line BL is decreased. Detection of the amount of charges remained on bit line BL thereafter enables the data reading.
Thus, according to the degree of injection of electrons
27
to floating gate
24
, data can be written into each memory cell MC in a non-volatile manner, and the stored data can be read out.
FIG. 11
shows distribution of threshold voltages Vth of memory cells in a flash memory.
Referring to
FIG. 11
, a memory cell in the data written state (in distribution
2
) with its stored data level being “0” has threshold voltage Vth higher than that of a memory cell in the data erased state (in distribution
1
) with its stored data level being “1”.
In respective memory cell groups in the data written state and in the data erased state, their threshold voltages Vth exhibit variation (e.g., from Va to Vb in distribution
2
). Therefore, to read out data from these memory cells, the data reading level should be set at a level enabling discrimination of the respective threshold voltages Vth in consideration of the variation therein. For example, the data reading level can be set to threshold voltage Va. In this case, the data level of a memory cell with its threshold voltage exceeding Va can be set to “0”, and the data level of a memory cell with its threshold voltage not greater than Va can be set to “1”.
In the case of multi-valued data of greater than 2 bits, distribution of threshold voltages Vth of the memory cells storing data in various levels should be tighter in consideration of variation thereof. That is, the variation of the threshold voltages in the respective levels of the data writing should be restricted more strictly.
A data writing sequence of a conventional flash memory will now be described with reference to FIG.
12
.
Referring again to
FIG. 11
, assume that a plurality of memory cells in the data erased state (in distribution
1
) are made to attain the data written state with their threshold voltages Vth falling within a range between Va (V) and Vb (V).
In a flash memory, a condition of data writing operation is set for each unit writing region that becomes a target of data writing operation at one time (or “unit writing operation”). Hereinafter, the prescribed unit region as the target of the unit writing operation is also referred to as a “sector”. One sector corresponds to a memory cell group selected by one word line.
When a data writing command is input, the data writing sequence starts at step S
1
. Here, the number of times of unit writing operations N is set to 1 (START).
Next, the data writing operation is carried out for each sector (step S
1
). The data writing condition will now be described.
In general, at the time of unit writing operation in the flash memory, a data writing pulse, or a voltage signal having prescribed voltage amplitude and pulse width, is applied to the control gate of a memory cell. In other words, the condition of the unit writing operation is set by the voltage amplitude VWW and the pulse width or application time tP of the data writing pulse.
FIG. 13
is a table for use in setting the condition of unit writing operation of the conventional data writing sequence. For example, when the number of times of unit writing operations having been conducted (hereinafter, also referred to as “unit writing operation total”) N is less than a prescribed number Y, the application time tP as the unit writing operation condition is set to T
1
. When unit writing operation total N is equal to prescribed number Y, application time tP is set to T
2
. When total N is greater than prescribed number Y, application time tP is set to T
2
×P
(N−Y)
(T
2
: initial term, P: power coefficient). Thus, application time tP increases exponentially after unit writing operation total N has exceeded prescribed number Y.
Next, to determine whether the data writing is properly conducted, a prescribed threshold voltage Vth=Va is applied to read data (step S
2
).
If all the memory cells have attained threshold voltages greate

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