Non-volatile semiconductor memory device with reduced chip...

Details Non-volatile semiconductor memory device with reduced chip... Non-volatile semiconductor memory device with reduced chip...

2006-11-07

2006-11-07

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120, C365S185130, C365S185170, C365S051000, C365S072000

Reexamination Certificate

active

07133314

ABSTRACT:
A semiconductor memory device that includes a memory cell array with memory cells arranged in rows and columns. The memory cells can also be formed in blocks. A plurality of word lines are applied voltages received by a plurality of drive lines, the plurality of word lines being classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than the arbitrary word line in the secondary adjacent word lines. A plurality of transfer transistors are utilized to select the plurality of word lines or blocks. Among the plurality of transfer resistors, transfer transistors for the residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for the arbitrary word line.

REFERENCES:
patent: 4347588 (1982-08-01), Hoffmann et al.
patent: 5619460 (1997-04-01), Kirihata et al.
patent: 6507508 (2003-01-01), Hosono et al.
patent: 2005/0013168 (2005-01-01), Futatsuyama et al.
patent: 2005/0058011 (2005-03-01), Futatsuyama et al.
patent: 2002-63795 (2002-02-01), None
patent: 2002-141477 (2002-05-01), None
patent: 95-10477 (1995-09-01), None
U.S. Appl. No. 11/346,293, filed Feb. 3, 2006, inventor Futatsuyama, et al.

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