Static information storage and retrieval – Floating gate – Particular connection
Patent
1991-08-15
1999-11-02
Zarabim, A.
Static information storage and retrieval
Floating gate
Particular connection
36518528, 36518529, G11C 1134
Patent
active
059782650
ABSTRACT:
An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.
REFERENCES:
patent: 4677590 (1987-06-01), Arakawa
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4962481 (1990-10-01), Choi et al.
patent: 4996669 (1991-02-01), Endoh
patent: 5008856 (1991-04-01), Iwahashi
patent: 5031011 (1991-07-01), Aritome et al.
patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5075890 (1991-12-01), Itoh et al.
IBM Technical Disclosure Bulletin, vol. 27, No. 6, Nov. 1984, New York, pp. 3302-3307; Adler, "Densely Arrayed EEPROM Havig Low Voltage Tunnel Write".
1988 Symposium On VLSI Technology, May 10, 1988, San Diego, CA, pp. 33-34; Shirota et al, "A New Nand Cell for Ultra High Density 5V Only EEPROMS".
International Electron Devices Meeting, Dec. 6, 1987, Washington, D.C., pp. 552-555; Masuoka et al, "New Ultra High Density EPROM and Flash EEPROM With Nand Structure Cell".
"A High Density EPROM Cell and Array", R. Stewart et al, RCA David Sarnoff Research Center, Route 1, Princeton, N.J. 08540 VII--9, pp. 89-90 Symposium on VLSI Technology Oiliest of Technical Papers, May 1986.
Aritome Seiichi
Itoh Yasuo
Kirisawa Ryouhei
Masuoka Fujio
Momodomi Masaki
Kabushiki Kaisha Toshiba
Zarabim A.
LandOfFree
Non-volatile semiconductor memory device with nand type memory c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory device with nand type memory c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device with nand type memory c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2144495