Non-volatile semiconductor memory device with improved layout

Details Non-volatile semiconductor memory device with improved layout Non-volatile semiconductor memory device with improved layout

1990-10-23

1992-11-24

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 502

Patent

active

051669005

ABSTRACT:
A non-volatile semiconductor memory device is fabricated on a semiconductor chip and comprises a memory cell array having a plurality of non-volatile memory cells arranged in rows and columns and occupying a first area, a row address decoder unit coupled through word lines to the rows of the non-volatile memory cells and responsive to row address bits for shifting one of the word lines to an active level, a column selector unit coupled through digit lines to the columns of the non-volatile memory cells and occupying a second area contiguous to the first area, a sense amplifier unit coupled through common digit lines to the column selector unit and occupying a third area contiguous to the second area, and a column address decoder unit responsive to column address bits and coupled through output lines to the column selector unit so that the digit lines are selectively coupled to the common digit lines, in which the sense amplifier unit and the column address decoder unit occupy a fourth area contiguous to the third area so that no rearrangement of the output lines is necessary for a new non-volatile semiconductor memory device increased in the number of the memory cells.

REFERENCES:
patent: 4700328 (1987-10-01), Burghard
patent: 4791607 (1988-12-01), Igarashi et al.

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