Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-01-28
1995-08-01
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
365218, 365900, G11C 700
Patent
active
054385440
ABSTRACT:
A non-volatile semiconductor memory device includes a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors. In an erase operation, the control circuit generates a voltage which is required for bringing memory cell transistors to an overerased state. In a write operation, the control circuit sets respective voltages of each control gate of memory cell transistors to be an identical one, and generates a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to present a first logic level. A second voltage is generated which is required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to present a second logic level. The control circuit further brings all of memory cell transistors included in a minimal block portion which is an object of erasure to an overerased state, by means of a flash erasure. It is therefore possible to realize a high speed erase operation and a high speed write operation.
REFERENCES:
patent: 5270979 (1993-12-01), Harari et al.
patent: 5295107 (1994-03-01), Okazawa et al.
IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 198, pp. 1259-1264 "A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory".
Dinh Son
Fujitsu Limited
Popek Joseph A.
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