Non-volatile semiconductor memory device with expected value...

Details Non-volatile semiconductor memory device with expected value... Non-volatile semiconductor memory device with expected value...

2006-02-14

2006-02-14

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120

Reexamination Certificate

active

06999347

ABSTRACT:
In response to a control command from a CPU, memory cell data read out from a memory cell is stored in a page buffer via a verify circuit. The page buffer provides page buffer data to the verify circuit. The verify circuit is added with the capability of carrying out expected value comparison with memory cell data, and can complete, concurrently during internal data readout, expected value comparison that was conventionally carried out with an external tester. The expected value comparison result of the verify circuit is output to an SR register as a verify determination signal.

REFERENCES:
patent: 6747894 (2004-06-01), Kawamura
patent: 6819596 (2004-11-01), Ikehashi et al.
patent: 6882569 (2005-04-01), Hosono et al.
patent: 9-259593 (1997-10-01), None
patent: 2001-155500 (2001-06-01), None

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