Non-volatile semiconductor memory device with defect detection

Details Non-volatile semiconductor memory device with defect detection Non-volatile semiconductor memory device with defect detection

2001-08-23

2002-11-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Data security

C365S185290, C365S210130

Reexamination Certificate

active

06483745

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application No. 2000-253194 filed Aug. 23, 2000, the content of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device such as, for example, an EEPROM (Electrically Erasable and Programmable Read-Only Memory) device.
2. Description of the Related Art
Conventionally, an EEPROM type memory device accumulates charges in a floating gate of a floating gate-type MOS transistor (hereinafter, referred to simply as a “transistor”) forming a memory cell, and stores data using a change in the threshold voltage value of the transistor which is caused by a change in the amount of the charges accumulated in the floating gate. However, in actual use, a phenomenon occurs that the charges accumulated in the floating gate escape via an insulating layer provided for insulating the floating gate from an electrode of the transistor. Such a phenomenon occurs because, for example, the insulating layer deteriorates over-time, and generates a data storage defect.
In order to prevent this phenomenon, the following techniques are used in general: (i) the insulating layer of the memory cell is reinforced during the production process of the EEPROM type memory device; and (ii) the voltage conditions for erasing and writing data are optimized so as to minimize a stress applied to the insulating layer when data is erased or written.
One example of the techniques (i) and (ii) is described in Japanese Laid-Open Publication No. 8-190796 entitled “Flash Memory Having Data Refreshing Function and Data Refreshing Method for Flash Memory”.
The above-mentioned publication discloses a method of detecting a memory cell, among a plurality of memory cells, in which charges have escaped from the floating gate and then rewriting data to the detected memory cell. According to this method, a reference cell for erasing and a reference cell for writing are used. When a memory cell is determined to be at a writing level using the reference cell for erasing, and when a memory cell is determined to be at an erasing level using the reference cell for writing, the memory cell is determined to be the defective memory cell in which charges have escaped from the floating gate.
In general, the escape of charges from the floating gate occurs most often among the defects involving the floating gate of an EEPROM type memory device. Other defects include an excessive increase in charges accumulated in the floating gate in the memory cell. By the above-described conventional method for detecting a memory storage defect, a cell in which the charges have been increased cannot be clearly distinguished from a cell in which the charges have escaped, and thus an increase in the charges is determined to be an escape of charges. In this specification, the defect that charges escape from a floating gate of a memory cell will be referred to as a “charge escaping defect”, and the defect that charges are excessively increased in a floating gate of a memory cell will be referred to as a “charge increasing defect”. The charge escaping defect and the charge increasing defect are both data storage detects.
In the case where no measure is taken against the charge escaping defect or the charge increasing defect, the following inconvenience occurs. The data storage characteristic of the memory device has a prescribed level immediately after the memory device is produced, but the insulating layer of the floating gate of the device tends to deteriorate as the device is used, especially as more and more data is erased from or written to the device. The level of data storage characteristic of the memory device is gradually decreased. In order to provide a memory device which is reliable for an extended period of time with certainty, it is necessary to accumulate a vast amount of know-how or expertise in terms of both designing and production, which is very difficult to realize.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a non-volatile semiconductor memory device for allowing a data writing operation to, a data reading operation from, and a data erasing operation from a plurality of non-volatile memory cells is provided. The non-volatile semiconductor memory device includes a data comparison section for outputting a first comparison result obtained by comparing data read from each of the plurality of memory cells and data read using a reference element for reading, a second comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for writing, and a third comparison result obtained by comparing data read from each of the plurality of memory cells and data read from a reference element for erasing; and a data storage defect detection section for detecting a data storage defect of a memory cell among the plurality of memory cell, based on the first, second and third comparison results obtained from the data comparison section.
In one embodiment of the invention, the data comparison section includes a reference element group including the reference element for reading, the reference element for writing, and the reference element for erasing; and a sensing differential amplification section connected to each of the plurality of memory cells, which are of an EEPROM type, at one input end of the section and also connected to the reference element group at the other input end of the section.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for writing, the data storage defect detection section determines that the memory cell has a charge escaping defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, the data storage detection section detects the data storage defect at least one of: during a non-selection period of each memory cell, during a blank period while normal data read is performed from each memory cell, and when power is turned on.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for writing, the data storage defect detection section determines that the memory cell has a charge escaping defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, when a threshold voltage value of a memory cell among the plurality of memory cells is between a threshold voltage value of the reference element for reading and a threshold voltage value of the reference element for erasing, the data storage defect detection section determines that the memory cell has a charge increasing defect.
In one embodiment of the invention, the non-volatile semiconductor memory device further includes a record information storage section for storing, as record information, memory cell information corresponding to the charge escaping defect and memory cell information corresponding to the charge increasing defect.
In one embodiment of the invention, when a threshold voltage value of a memo

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