Non-volatile semiconductor memory device with accelerated...

Details Non-volatile semiconductor memory device with accelerated... Non-volatile semiconductor memory device with accelerated...

2005-01-18

2005-01-18

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185220, C365S185330, C365S185120

Reexamination Certificate

active

06845041

ABSTRACT:
A non-volatile semiconductor memory device of the present invention employs an acceleration technique for shortening a column scanning time. The acceleration technique can be realized by adjusting the width of an internal data bus, the adjusted width being selectively used according to an operation mode. When a normal read operation is executed, for example, a NAND-type flash memory device has an internal data bus width corresponding to the data input/output width. When an erase/program verify operation is executed, a NAND-type flash memory device has a wider internal data bus width than the data input/output width. According to the acceleration technique, it is possible to prevent any increase in the column scanning time in proportion to an increase in page size.

REFERENCES:
patent: 5712818 (1998-01-01), Lee et al.
patent: 5920503 (1999-07-01), Lee et al.
patent: 6011720 (2000-01-01), Tanaka
patent: 2001-023382 (2001-01-01), None
English language of Abstract for Japanese patent publication No. 2001-023382.

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device with accelerated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device with accelerated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device with accelerated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3427422