Non-volatile semiconductor memory device with a memory array...

Details Non-volatile semiconductor memory device with a memory array... Non-volatile semiconductor memory device with a memory array...

2002-05-16

2003-09-09

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185240, C365S185290

Reexamination Certificate

active

06618286

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to the memory array structure of a flash memory.
2. Description of the Background Art
Recently, a flash memory capable of non-volatile data storage (batch-erasable, electrically rewritable read only memory) goes mainstream. In particular, a MONOS (Metal Oxide Nitride Oxide Silicon) memory transistor cell has attracted attention in such a flash memory because of its low costs, small area, and charge storage portion. The MONOS memory transistor cell is characterized in that a nitride film is used as the charge storage portion instead of a floating gate used in the conventional examples.
The MONOS memory transistor cell is different from the floating gate: structure in that the polycrystalline silicon of floating gate is replaced with a nitride film.
FIGS. 10A
,
10
B and
10
C illustrate normal write, read and erase operations of the MONOS memory transistor cell, respectively.
Referring to
FIGS. 10A
,
10
B and
10
C, MONOS memory transistor cell MC is formed from a stacked layer of three insulating films (i.e., an oxide film;
4
, a nitride film
5
, and an oxide film
6
) and a polycrystalline silicon of control gate
7
on a P-type semiconductor substrate
1
. Near the stacked gate on P-type semiconductor substrate
1
, N-channel diffusion regions
2
,
3
are formed in a self-aligned manner. Memory transistor cell MC thus corresponds to an N-channel field effect transistor formed on P-type semiconductor substrate
1
.
FIG. 10A
illustrates normal write operation of MONOS memory transistor cell MC.
When 0 V is applied to P-type semiconductor substrate 1, 10 V is applied to control gate
7
, 5 V is applied to diffusion region
2
, and 0 V is applied to diffusion region
3
, channel electrons are accelerated by a steep electric field created in diffusion region
2
of the memory transistor cell. Those accelerated electrons which overcome the barrier height of the oxide film are trapped on the side of diffusion region
2
in nitride film
5
(bit
1
). As a result, the threshold voltage of memory transistor cell MC is increased to render memory transistor cell MC in the written state storing data “0”. For example, the data of bit
1
is “0” in the written state caused by the trapped electrons, and “1” in the state where no data is written (i.e., in the erased state). The following description is given on the assumption that the data is “0” in the written state and “1” in the erased state.
When the applied voltages to diffusion regions
2
,
3
are reversed, i.e., when 0 V is applied to diffusion region
2
and 5 V is applied to diffusion region
3
as shown in parentheses in
FIG. 10A
, the electrons are trapped on the side of diffusion region
3
in nitride film
5
(bit
2
). As a result, the threshold voltage of memory transistor cell MC is increased to render memory transistor cell MC in the written state storing data “0”. Accordingly, the data of bit
2
is “0” in the written state caused by the trapped electrons, and “1” in the erased state.
This MONOS structure traps electrons in non-covalent bonds (dangling bonds) that are distributed in nitride film
5
at random. Electrons are stored at different positions in nitride film
5
(i.e., on the sides of diffusion regions
2
and
3
in nitride film
5
) one bit each, enabling two-bit/cell data storage.
FIG. 10B
illustrates read operation of MONOS memory transistor cell MC.
First, operation of reading bit
1
on the side of diffusion region
2
in nitride film
5
will be described.
A voltage of 0 V is applied to P-type semiconductor substrate
1
, 3 V is applied to control gate
7
, 0 V is applied to diffusion region
2
, and 2 V is applied to diffusion region
3
. It is herein assumed that memory transistor cell MC is in the written state on the side of diffusion region
2
in nitride film
5
, that is, electrons have been trapped in nitride film
5
. In this case, a high threshold voltage inhibits memory transistor cell MC from being turned ON, and no current path is formed from diffusion region
3
to diffusion region
2
. As a result, “0” can be read as the data of bit
1
. On the other hand, when memory transistor cell MC is in the erased state on the side of diffusion region
2
in nitride film
5
, a low threshold voltage allows memory transistor cell MC to be turned ON, and a current path is formed from diffusion region
3
to diffusion region
2
. As a result, “1” can be read as the data of bit
1
.
Hereinafter, operation of reading the data of bit
2
on the side of diffusion region
3
in nitride film
5
will be described.
The applied voltages to diffusion regions
2
,
3
are reversed. More specifically, 0 V is applied to P-type semiconductor substrate
1
, 3 V is applied to control gate
7
, 2 V is applied to diffusion region
2
, and 0 V is applied to diffusion region
3
, as shown in parentheses in FIG.
10
B. It is herein assumed that memory transistor cell MC is in the written state on the side of diffusion region
3
in nitride film
5
, that is, electrons have been trapped in nitride film
5
. In this case, a high threshold voltage inhibits memory transistor cell MC from being turned ON, and no current path is formed from diffusion region
2
to diffusion region
3
. As a result, “0” can be read as the data of bit
2
. On the other hand, when memory transistor cell MC is in the erased state on the side of diffusion region
3
in nitride film
5
, a low threshold voltage allows memory transistor MC to be turned ON, and a current path is formed from diffusion region
2
to diffusion region
3
. As a result, “1” can be read as the data of bit
2
.
Accordingly, by adjusting the applied voltages to diffusion regions
2
,
3
, bit
1
and bit
2
can be read according to whether a current path is formed or not. This enables two-bit/cell read operation.
FIG. 10C
illustrates erase operation of MONOS memory transistor cell MC.
First, operation of erasing bit
1
on the side of diffusion region
2
in nitride film
5
will be described.
It is herein assumed that 0 V is applied to P-type semiconductor substrate
1
and control gate
7
, 10 V is applied to diffusion region
2
, and diffusion region
3
is in the open state (OPEN).
In this case, it flows a Fowler-Nordheim current from bit
1
on the side of diffusion region
2
trapped the electrons in nitride film
5
to substrate region
1
or diffusion region
2
. The electrons are thus removed from the side of diffusion region
2
in nitride film
5
. In this state, memory transistor cell MC has a reduced threshold voltage.
Hereinafter, operation of erasing bit
2
on the side of diffusion region
3
in nitride film
5
will be described.
It is herein assumed that 0 V is applied to P-type semiconductor substrate
1
and control gate
7
, 10 V is applied to diffusion region
3
, and diffusion region
2
is in the open state, as shown in parentheses in FIG.
10
C.
In this case, it flows a Fowler-Nordheim current from bit
2
on the side of diffusion region
3
trapped the electrons in nitride film
5
to substrate region
1
or diffusion region
3
. The electrons are thus removed from the side of diffusion region
3
in nitride film
5
. In this state, memory transistor cell MC has a reduced threshold voltage.
Note that, when 10 V is applied to both diffusion regions
2
,
3
, electrons are removed from both bits
1
,
2
. The data is erased in this way.
FIG. 11
shows the structure of an array of a flash memory using the above MONOS memory transistor cells MC (hereinafter, referred to as NROM(R) memory array).
Referring to
FIG. 11
, the NROM(R) memory array includes identical memory block units MBU arranged in a matrix. Adjacent two memory block units MBU are electrically coupled to each other.
Memory block unit MBU
1
located in the center will now be described. Since the other memory block units MBU have the same circuit structure as that of memory block unit MBU
1
, deta

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