Non-volatile semiconductor memory device that can be...

Details Non-volatile semiconductor memory device that can be... Non-volatile semiconductor memory device that can be...

2003-07-23

2004-07-06

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185110, C365S185230

Reexamination Certificate

active

06760259

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly to a flash memory that can have the erasure unit block configuration modified.
2. Description of the Background Art
From the functional perspective, a flash memory is a collective erasure type non-volatile semiconductor memory device capable of electrical programming and erasure. The demand for flash memories in portable equipment and the like is great by virtue of its low cost and electrical erasure function, leading to active research and development. A flash memory employs as a memory cell a transistor including, for example, a floating gate to alter the threshold voltage (referred to as memory transistor, hereinafter).
FIG. 26
shows an array configuration of a conventional flash memory.
For the sake of simplification, a memory array of 8 M bits as a whole will be described with reference to
FIG. 26. A
memory array
500
includes blocks B
000
-B
007
, each block formed of memory cells corresponding to 4 k words (64 k bits), blocks B
008
-B
022
, each block formed of memory cells corresponding to 32 k words (512 k bits), and a block B
100
. Each of blocks B
000
-B
022
corresponds to a basic unit of erasure operation in a flash memory.
Flash memories often require a region of 4 k words. Therefore, memory array
500
includes blocks B
000
-B
007
having a storage capacity smaller than that of a general data storage region. Such regions of 4 k words are called, for example, “boot blocks” or “parameter blocks”.
A boot block is a region read by the CPU of a system mounted with a flash memory at the start of the system immediately after power is turned on. A parameter block is a region where data expected to be rewritten frequently is temporarily written. The block having the storage capacity of 32 k words is used as the region to store general data and programs. A flash memory must incorporate blocks differing in size depending upon the application.
Block B
100
is a region equivalent to blocks B
000
-B
007
from the address allocation perspective, and is a non-used region. Memory block B
100
, even though not used, has a configuration similar to that of each of blocks B
008
-B
022
since continuity of signals on the memory array must be maintained.
The selection of a memory block is effected by block select signals BAVS
0
, BAVS
1
, and BAVM
0
-BAVM
3
to select a block vertical position, and block select signals BAH
0
-BAH
3
to select a block horizontal position. When a vertical block position and a horizontal block position are both rendered active, the block corresponding to a crossing thereof is selected. For example, when block B
008
is to be selected, select signals BAVM
0
and BAH
1
are rendered conductive whereas the remaining select signals are rendered inactive.
FIG. 27
is a block diagram of a configuration of a conventional block select decoder generating a memory block select signal.
Referring to
FIGS. 26 and 27
, a block select decoder
502
generates block select signals BAV
0
, BAVS
1
, BAVM
0
-BAVM
3
, and BAH
0
-BAH
3
using address bits A
12
-A
18
of an externally applied address signal. Block select decoder
502
includes a 4-input NOR circuit
562
receiving address bits A
15
, A
16
, A
17
and A
18
to output a select signal BOP, a vertical block select circuit
564
providing select signals BAVS
0
, BAVS
1
, and BAVM
0
-BAVM
3
of the vertical position in accordance with address bits A
14
, A
17
, A
18
and select signal BOP, and a horizontal block select signal
566
providing select signals BAH
0
-BAH
3
of the horizontal position in accordance with address bits A
12
, A
13
, A
15
and A
16
and select signal BOP.
Vertical block select circuit
564
includes an address decode unit
582
rendered active in accordance with select signal BOP to decode address bit A
14
and output signals BAVS
0
, BAVS
1
, and an address decode unit
584
operating when select signal BOP is inactive and ceasing operation when select signal BOP is rendered active. Address decode unit
584
decodes address bits A
17
and A
18
when active to output signals BAVM
0
-BAVM
3
.
Horizontal block select circuit
566
includes an address select unit
610
providing address bits A
12
and A
13
as select address bits SA
0
, SA
1
when select signal BOP is rendered active, and providing address bits A
15
and A
16
as select address bits SA
0
, SA
1
when select signal BOP is inactive and an address decode unit
612
decoding select address bits SA
0
, SA
1
to output signals BAH
0
-BAH
3
.
In the case of a memory array of 8 M bits shown in
FIG. 26
, the address bits selecting a 32 k-word block are A
15
, A
16
, A
17
and A
18
in a 1-word 16-bit structure. The address bits selecting a 4 k-word block are A
12
, A
13
and A
14
. The conventional example described here is based on a configuration in which four memory blocks are disposed in the horizontal direction as shown in FIG.
26
.
First, activation/inactivation of signal BOP selecting a 4 k-word region is determined by NOR circuit
562
.
When an address corresponding to memory blocks B
008
-B
022
is input, signal BOP is rendered inactive, whereby address decode unit
582
renders signals BAVS
0
and BAVS
1
inactive, whereas address decode unit
584
renders active one of select signals BAVM
0
-BAVM
3
of the vertical memory blocks active in accordance with address bits A
17
and A
18
.
In this case, address select unit
610
outputs address bits A
15
and A
16
as select address bits SA
0
and SA
1
. Therefore, address decode unit
612
decodes address bits A
15
and A
16
to render active one of select signals BAH
0
-BAH
3
.
When all address bits A
15
-A
18
are at an L level (logical low), select signal BOP is rendered active. This indicates that an address is input corresponding to non-used memory block B
100
of FIG.
26
. In this case, a corresponding region of memory blocks B
000
-B
007
is selected instead of selecting memory block B
100
. Specifically, when signal BOP is rendered active, address decode unit
584
is rendered inactive, and signals BAVM
0
-BAVM
3
are rendered inactive. Then, address decode unit
582
decodes address bit A
14
to render active one of signals BAVS
0
and BAVS
1
.
When signal BOP is active, address select unit
610
outputs address bits A
12
and A
13
as select address bits SA
0
and SA
1
. Therefore, address decode unit
512
decodes address bits A
12
and A
13
to render active one of signals BAH
0
-BAH
3
.
Conventionally, the block division and address allocation determined by block select decoder
502
are always fixed. In other words, the region of 8 M bits was handled as eight blocks of a 4 k-word block and fifteen blocks of a 32 k-word block B
008
-B
022
, i.e., a total of 23 blocks.
Thus, memory array
500
of
FIG. 26
includes 23 blocks of memory blocks B
000
-B
022
to be used. This means that an erasure operation must be designated from outside the chip 23 times in order to erase the entire memory array of 8 M bits.
In
FIG. 26
the eight blocks of 4 k word blocks, i.e. blocks B
000
-B
007
, are allocated the least significant side of the address. This is termed a “bottom boot type”. However, there is a case where a top boot type flash memory having the blocks of 4 k words allocated the most significant side of the address is required, depending upon the system employed. In order to modify a bottom boot type memory into a top boot type memory for usage, the conventional approach was to invert a particular address bit in an address input buffer.
FIG. 28
is a circuit diagram showing a configuration of such a conventional address input buffer
516
.
Referring to
FIG. 28
, address input buffer
516
includes address inversion circuits
520
,
522
and
524
switching the non-inversion/inversion of address bits A
15
, A
16
and A
17
in accordance with a signal TOP rendered active when the memory is switched to a top boot type memory for usage.
Address inversion circuit
520
includes an inverter receiving and inverting an ext

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