Non-volatile semiconductor memory device improved sense...

Details Non-volatile semiconductor memory device improved sense... Non-volatile semiconductor memory device improved sense...

2001-08-20

2003-01-07

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189070, C365S203000

Reexamination Certificate

active

06504761

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more particularly, to a configuration for reading data of a non-volatile memory cell.
2. Description of the Background Art
A sense amplification configuration in a conventional non-volatile semiconductor memory device will be described. Referring to
FIG. 14
, a non-volatile memory cell MC is connected to a detecting unit
50
via a Y gate M
5
(NMOS transistor).
Detecting unit
50
includes an NMOS transistor M
2
, an inverter I
1
, PMOS transistors M
1
and M
3
, and an NMOS diode M
4
.
Inverter I
1
inverts a signal on a bit line BL. Transistor M
2
is connected between a node N
1
and bit line BL, and has its gate receiving an output of inverter I
1
.
Transistor M
1
is connected between a power supply node Vcc and node N
1
, and has its gate connected to node N
1
. Transistor M
3
is connected between power supply node Vcc and an output node N
2
, and has its gate connected to node N
1
. Transistors M
1
and M
3
constitute a current mirror.
NMOS diode M
4
is connected between node N
2
and a ground node GND that receives a ground voltage. A detected current flowing through transistor M
3
is converted to a voltage by NMOS diode M
4
.
When a word line WL is selected and Y gate M
5
is closed according to a gate signal YG, detecting unit
50
detects a current of memory cell MC, and the detected current is converted to a voltage. The detected data (voltage) is output from node N
2
. Thus, the data value of the memory cell is determined.
With the sense amplification configuration described above, however, transistor M
3
is turned on during a precharging (charging) period of the bit line, as node N
1
attains an intermediate voltage between 0 V and power supply voltage Vcc. This allows a current flow from power supply node Vcc through transistors M
3
and M
4
to ground node GND, thereby increasing current consumption.
One way to improve such a sense amplification configuration is shown in FIG.
15
. In the configuration shown in
FIG. 15
, a cut transistor (PMOS transistor) M
6
′ is connected between node N
1
and power supply node Vcc. Transistor M
6
′ is turned on/off according to a control signal PC. During the precharging period of the bit line, control signal PC is set to “L”, so that transistor M
6
′ is turned on, and node N
1
attains a power supply voltage level Vcc. When transistor M
6
′ turns on, transistor M
3
turns off. Accordingly, a current is prevented from flowing through transistors M
3
and M
4
, which reduces current consumption during the precharging period.
Assume, however, the case where control signal PC is set to power supply voltage level Vcc after completion of the precharging to turn off transistor M
6
′, and then data of memory cell MC is read out while memory cell MC is in a state allowing a current flow therethrough (i.e., a stored state). In such a case, it would take a long time before the voltage of node N
1
changes from power supply voltage level Vcc to a voltage level Vsense at which the read data can be determined.
Thus, data cannot be read out at high speed with just the sense amplification configuration as described above. Further, a high-precision data reading operation cannot be assured with such a sense amplification configuration.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile semiconductor memory device that permits reduction of current consumption, high-speed operation and high-precision reading.
The non-volatile semiconductor memory device according to an aspect of the present invention includes: a non-volatile memory cell; a word line corresponding to the memory cell; a bit line corresponding to the memory cell; and a detecting unit connected to the bit line and detecting stored data in the memory cell. The detecting unit includes: a current mirror formed of first and second transistors each connected to a power supply voltage node, detecting a current of the memory cell; a transistor diode-connected between the power supply voltage node and gates of the first and second transistors; and a current-voltage converting element converting the current detected by the current mirror to a voltage.
Preferably, the diode-connected transistor precharges the gates of the first and second transistors to a voltage level that is lower than the power supply voltage level.
In particular, the detecting unit further includes a cut transistor connected between the diode-connected transistor and the power supply voltage node.
In particular, the detecting unit further includes a bypass transistor connected between the gates of the first and second transistors and the power supply voltage node.
Preferably, the detecting unit further includes a cut transistor connected between the diode-connected transistor and the power supply voltage node, and a bypass transistor connected between the gates of the first and second transistors and the power supply voltage node. The cut transistor and the bypass transistor are turned on/off so as to reduce a precharging time of the bit line.
In particular, at the time of precharging the bit line, after the cut transistor and the bypass transistor are both turned on, the cut transistor is turned off earlier than the bypass transistor.
Preferably, the current-voltage converting element is connected to the second transistor at an output node outputting the stored data. The detecting unit further includes a cut transistor connected between the power supply voltage node and the second transistor. Alternatively, the detecting unit may further include a cut transistor connected between the current-voltage converting element and a ground node.
The non-volatile semiconductor memory device according to another aspect of the present invention includes: a non-volatile memory cell; a first bit line corresponding to the memory cell; a non-volatile reference cell; a second bit line corresponding to the reference cell; a first detecting unit, having a first current mirror therein, detecting stored data of the memory cell through the first bit line; a second detecting unit, having a second current mirror therein, detecting stored data of the reference cell through the second bit line; and a differential amplification unit that detects a difference between an output of the first detecting unit and an output of the second detecting unit to determine the stored data of the memory cell. The first and second detecting units are made to operate at different timings such that the precharging periods for the first and second bit lines become different from each other.
Preferably, the operating period of the second current mirror is shorter than the operating period of the first current mirror.
In particular, the first current mirror includes first and second transistors, and the second current mirror includes third and fourth transistors. The first detecting unit further includes a fifth transistor that is connected between the gates of the first and second transistors and a first power supply voltage node. The second detecting unit further includes a Id sixth transistor that is connected between the gates of the third and fourth transistors and a second power supply voltage node.
Preferably, the differential amplification unit starts an operation between the timing at which the first current mirror starts to operate and the timing at which the second current mirror starts to operate.
In particular, the differential amplification unit includes a differential amplification circuit that outputs a difference between the outputs of the first and second detecting units, an output node connected to the output node of the differential amplification circuit and outputting data of the memory cell, and a setting circuit connected to the output node and setting an initial state of the output node to a prescribed potential. The initial state is a state of the output node that would be obtained when a prescribed second current mirror is made to ope

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