Static information storage and retrieval – Powering
Reexamination Certificate
2001-10-18
2003-08-05
Le, Thong (Department: 2818)
Static information storage and retrieval
Powering
C365S230030, C365S185110
Reexamination Certificate
active
06603700
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a rewritable non-volatile semiconductor memory device having a plurality of memory banks.
The rewritable non-volatile semiconductor memories can be roughly divided into FN (Fowler-Nordheim) erase/CHE (Channel Hot Electron) write type EEPROMs (Electrically Erasable Programmable Read Only Memories) and FN erase/FN write type EEPROMs. Since the FN erase/FN write type EEPROM consumes a very small amount of current in write operation, a large number of bits can be written at a time. This reduces the write time per bit, which is effective in a memory having larger capacitance. For example, even if the write time per bit is 1 ms, simultaneously writing 1,024 bits would result in 0.97 &mgr;s per bit, and simultaneously writing 8,192 bits would result in 0.12 &mgr;s per bit, enabling a higher write operation speed than in the case where 32 bits are simultaneously written with 10 &mgr;s in the CHE mode (0.31 &mgr;s per bit).
In order to write the data to a multiplicity of memory cells simultaneously, it is desirable that the memory cells to be written are connected to a common word line. However, a memory array must be divided in view of storage of the write data and fast reading of the memory array.
Moreover, such an FN erase/FN write type semiconductor memory requires a high voltage (e.g., 9 V) and thus requires a power supply circuit for boosting a low power supply voltage (e.g., 2.5 V). For example, in the FN erase/FN write type memory, a voltage of −9.0 V is applied to a substrate and source lines in a memory array to be erased at a time, a voltage of +8.0 V is applied to word lines therein, and drains therein are rendered in a floating state. Every memory cell in the memory array to be erased at a time is rendered to have an increased threshold value. In write operation, a voltage of 0 V is applied to the substrate and the source line of a memory cell to be written, and a voltage of −9.0 V is applied to a word line (control gate) thereof. Moreover, a voltage of 6.0 V is applied to the drain of the memory cell to be written, and a voltage of 0.0 V is applied to the drain of a memory cell that is not to be written. The memory cell thus written has a reduced threshold value, and the threshold value of the non-written memory cell remains high.
In such write operation, setting the drain voltage of the memory cell to be written to a high voltage according to the write data and setting the drain voltage of the memory cell that is not to be written to a low voltage enables writing to all the memory cells on the same word line. Moreover, even if the memory array is divided into a plurality of banks, providing each bank with a write circuit would enable simultaneous writing to a multiplicity of memory cells included in the plurality of banks.
However, in order to write to a multiplicity of memory cells simultaneously, the power supply circuit for supplying a high voltage required for writing/erasing must have increased current supply capability. On the other hand, even in the situation where rewriting is not conducted, there is a case where a boosted power supply voltage is supplied also in read operation, for example, in order to increase the read speed even in low-voltage operation. In such a case, supplying a voltage from the power supply circuit with its current supply capability increased in order to write to a multiplicity of memory cells simultaneously would result in increased power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile semiconductor memory device capable of reducing power consumption.
According to one aspect of the present invention, a non-volatile semiconductor memory device includes a first memory bank, a second memory bank, a first power supply circuit and a second power supply circuit. The first power supply circuit supplies to the first memory bank a boosted voltage for writing to a memory cell in the first memory bank in write operation. The second power supply circuit supplies to the second memory bank a boosted voltage for writing to a memory cell in the second memory bank in write operation, and supplies to the first and second memory banks a boosted voltage for reading from a memory cell in the first and second memory banks in read operation.
In the above non-volatile semiconductor memory device, in write operation, the first power supply circuit supplies the boosted voltage for writing to the first memory bank, and the second power supply circuit supplies the boosted voltage for writing to the second memory bank, enabling sufficient current supply capability to be assured. On the other hand, in read operation, only the second power supply circuit supplies the boosted voltage for reading to the first and second memory banks, enabling reduction in power consumption.
According to another aspect of the present invention, a non-volatile semiconductor memory device for simultaneously writing to a plurality of memory banks in write operation, and selectively reading from at least one of the plurality of memory banks in read operation includes a first memory bank, a second memory bank, a first power supply circuit, a second power supply circuit and a supply control circuit. The first power supply circuit outputs a boosted voltage for writing to a memory cell in the first memory bank in write operation. The second power supply circuit outputs a boosted voltage for writing to a memory cell in the second memory bank in write operation, and outputs a boosted voltage for reading from a memory cell in the first and second memory banks in read operation. The supply control circuit supplies the boosted voltage for writing from the first power supply circuit to the first memory bank as well as supplies the boosted voltage for writing from the second power supply circuit to the second memory bank in write operation, and supplies the boosted voltage for reading from the second power supply circuit to the first and second memory banks in read operation.
In the above non-volatile semiconductor memory device, in write operation, the boosted voltage for writing from the first power supply circuit is supplied to the first memory bank, and the boosted voltage for writing from the second power supply circuit is supplied to the second memory bank, enabling sufficient current supply capability to be assured. In read operation, the boosted voltage for reading from the second power supply circuit is supplied to the first and second memory banks, in other words, the first power supply circuit does not supply any boosted voltage to the memory banks in read operation, enabling reduction in power consumption.
Preferably, the supply control circuit includes a first switch, a second switch and a third switch. The first switch is connected between the first memory bank and the first power supply circuit. The second switch is connected between the second memory bank and the second power supply circuit. The third switch is connected between the first memory bank and the second power supply circuit.
In the above non-volatile semiconductor memory device, in write operation, the first switch and the second switch are turned ON, and the third switch is turned OFF. Accordingly, the boosted voltage for writing from the first power supply circuit is supplied to the first memory bank through the first switch while the boosted voltage for writing from the second power supply circuit is supplied to the second memory bank through the second switch. On the other hand, in read operation, the first switch is turned OFF, and the second switch and the third switch are turned ON. Accordingly, the boosted voltage for reading from the second power supply circuit is supplied to the first memory bank and the second memory bank through the third switch and the second switch, respectively.
Preferably, the first power supply circuit is stopped in read operation. This reduces power cons
Le Thong
Matsushita Electric - Industrial Co., Ltd.
McDernott, Wil & Emery
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