Non-volatile semiconductor memory device having memory cells, ea

Details Non-volatile semiconductor memory device having memory cells, ea Non-volatile semiconductor memory device having memory cells, ea

1994-03-23

1995-09-12

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 365218, G11C 1156

Patent

active

054503418

ABSTRACT:
A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating gate for setting a given threshold voltage in the memory cell. In addition, a non-volatile semiconductor memory device capable of checking if the data stored in the selected memory cell is correct by using one of at least two binary bits of the data as a parity bit, and a method of writing or reading data in or from that memory device.

REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5119330 (1992-06-01), Tanagawa
patent: 5287305 (1994-02-01), Yoshida
A 16kb Electrically Erasable Non-Volatile Memory, Johnson et al., 1980, IEEE, ISSCC, Dig. Tech. PAP. pp. 152-153, 271.
Analysis and Modeling of Floating-Gate EEPROM Cells, Kolodny et al., IEEE Trans., Electron Devices, Jun. 1986, ED-33, No. 6, pp. 835-844.
Semiconductor MOS Memory and Method of Using the Same, Nikkan Kogyo Newspaper Co., 1990, pp. 96-101.
A novel Cell Structure Suitable For a 3 Volt Operation, Sector Erase Flash Memory, Onoda et al., IEDM 1992, pp. 509-602.

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