Non-volatile semiconductor memory device having memory...

Details Non-volatile semiconductor memory device having memory... Non-volatile semiconductor memory device having memory...

2002-12-23

2004-08-17

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185240

Reexamination Certificate

active

06778443

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-392712, filed Dec. 25, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly to, an erasing function of a flash memory.
2. Description of the Related Art
A flash memory has been suggested which simultaneously erases data stored in a memory cell array, as a conventional non-volatile semiconductor memory device. An erase sequence of a conventional NOR-type flash memory is shown in FIG.
13
. By the sequence, erase-unit blocks are selected sequentially and, to have data stored therein erased, undergo a pre-programming sub-sequence and an erase sub-sequence consecutively. Here, pre-programming refers to putting all the memory cells in a block into a written-in state (state “0”) in order to execute the erase uniformly.
That is, as shown in
FIG. 13
, for example, to erase data stored in three blocks of first, second, and third blocks, after erase execution is confirmed, the first block is pre-programmed and subsequently undergoes data erase and then, after the erase is confirmed, the second block is pre-programmed and subsequently undergoes data erase. After the erase is confirmed, the third block is pre-programmed and subsequently undergoes data erase. When n number of blocks are provided, similarly, each time erase execution is confirmed, a sequence of pre-programming and data erase is executed.
In this case, the process checks for whether a given block is selected by a command to undergo data erase or to be protected therefrom (data erase-inhibited) and, if it is not to undergo data erase, does not pre-program the block and, otherwise, pre-programs it.
Furthermore, pre-programming is executed for each address or for a few addresses sequentially by counting up row and column addresses in a relevant block.
Upon completion of pre-programming of all the memory cells in the block, the process confirms the final address to then execute data erase.
FIGS. 14A-14C
show one example of a method of executing write-in (programming) on transistors making up a memory cell and applying an erasing bias thereon. In this case, in order to apply the erasing bias, a high electric field is applied between a silicon substrate and a word line, instead of which, however, such a method may be used as to apply a high electric field between a word line and a source in order to execute data erase.
A memory cell shown in
FIGS. 14A-14C
comprises a source
102
, a drain
103
, a floating gate
104
, and a control gate
105
which are formed in or on a silicon substrate
101
.
The programming is executed by applying a program bias such as shown in
FIG. 14A
to the memory cell to inject hot electrons from a side of the drain
103
formed in the silicon substrate
101
into the floating gate
104
so that they may be trapped therein. In this case, a large current flows into each memory cell, so that the programming cannot be executed on a number of memory cells simultaneously.
The erase is executed as verifying it for each bit. It is to be noted that pre-programming may also be executed as verifying it for each bit.
In verification, if even one bit of memory cell encounters a verification failure (state where data in the memory cell is not completely erased), the process applies such an erasing bias as shown in
FIG. 14B
again on all the memory cells in a relevant block and releases electrons trapped in the floating gate
104
into the silicon substrate
101
, thus erasing data stored in the memory cells simultaneously. The process repeats this simultaneous data erase and verification process until all the memory cells in the block pass the verification step.
Furthermore, in verification, until it confirms the final address, the process counts up the row/column addresses in a relevant block using an address count-up step. When it has completed simultaneous data erase and verification of the relevant block, the process subsequently carries out a series of erase sequences on a block to undergo data erase next.
In such a manner, the process repeats pre-programming, simultaneous erase, and verification for each of the blocks until it confirms the final block and then ends the erase sequence.
FIG. 15
shows a diagram of an equivalent circuit of a NOR-type flash memory array. The NOR-type flash memory shown in
FIG. 15
comprises a memory cell M
i,j
(i=1, 2 and j=1, 2), a selection gate S
i
, a word line WL
i
(which is shown in the case of i=1, 2), a bit line BL, and a source line S.
Since the NOR-type flash memory has such an array configuration as shown in
FIG. 15
, if the threshold value of a memory cell is reduced excessively because of the erase, the bit line BL is supplied with a current nevertheless the word line WL
i
is in an unselected state at the low level (“L”), so that there are some cases where “1” is always read out despite that a word line other than WL
i
is selected. In such a case, therefore, weak programming is executed after the erase.
For example, if, as shown in
FIG. 14C
illustrating a convergence bias, only the bit line is supplied with a high voltage (where the drain
103
is at 5V) in a condition where the word lines are all in an unselected state (where the control gate
105
is at 0V), a current is concentrated to such a memory cell of those on the same bit line as to have a lower threshold value due to the excessive erase, so that this overerased memory cell can be given a little higher threshold voltage.
In the case of a program bias shown in
FIG. 14A
, the programming ends in 5-10 &mgr;s, whereas in the case of an erasing bias shown in
FIG. 14B
, the erase takes 10-100 ms to be completed. As a result, in the case of a 64K byte-block, for example, it takes 500-1000 ms of time to complete an erase sequence.
As described above, the conventional non-volatile semiconductor memory device has a sequence for executing pre-programming and subsequent erase for each block and, therefore, has a long time required to complete the erase sequence.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a non-volatile semiconductor memory device comprises:
a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time;
a sense amplifier; and
an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
According to a second aspect of the present invention, a non-volatile semiconductor memory device comprises:
a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time;
a sense amplifier; and
an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells in a predetermined number of blocks after pre-programming, the predetermined number of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
According to a third aspect of the present invention, a method for executing an erase sequence on a non-volatile semiconductor memory device including a plurality of blocks each having a plurality

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