Non-volatile semiconductor memory device having means to latch t

Details Non-volatile semiconductor memory device having means to latch t Non-volatile semiconductor memory device having means to latch t

1988-10-11

1989-12-12

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Byte or page addressing

36518911, 36518905, 36523008, 365218, G11C 700, G11C 800

Patent

active

048872423

ABSTRACT:
There is disclosed a non-volatile semiconductor memory device provided with column latching circuits each temporally memorizing plural bytes of input data bits, and gate and drain voltage levels of each of memory cell transistors are controlled on the basis of the input data bits latched into the column latching circuits for a simultaneous write-in operation, so that only column address selecting lines and row address lines are provided for specifying a plurality of memory cell groups in the simultaneous write-in operation.

REFERENCES:
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4771404 (1988-09-01), Mano et al.

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