Non-volatile semiconductor memory device having electrically...

Details Non-volatile semiconductor memory device having electrically... Non-volatile semiconductor memory device having electrically...

1999-03-01

2001-12-11

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185210, C365S185220, C365S185280

Reexamination Certificate

active

06330186

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of programming and a method of reading out from a non-volatile semiconductor memory device, and more specifically to a method of programming data into a non-volatile memory matrix array, and to a non-volatile semiconductor memory device that has a characteristic method of reading data from a non-volatile memory matrix array, and which is particularly suitable for application to a high-speed readout system.
Additionally, the present invention relates to the circuit configuration of a non-volatile semiconductor memory and to a characteristic program method for deleting data from and writing data to a memory array with high speed, and in particular to a non-volatile semiconductor memory device which can be electrically overwritten.
BACKGROUND ART
FIG. 4
is a drawing which shows the configuration of a non-volatile semiconductor memory device of the past. First, the configuration of a non-volatile semiconductor memory device of the past will be described, with reference made to FIG.
4
.
As shown in
FIG. 4
, the non-volatile semiconductor memory device has a control circuit
11
, a memory matrix array
13
, a row address selection circuit
15
, a column address selection circuit
17
, a column direction first program circuit
19
, a row direction second program circuit
21
, a differential sense amplifier circuit
23
, an address decoder circuit
25
, a comparison reference voltage generation circuit
27
, and a data input/output switching circuit
29
.
The control circuit
11
is connected to the row address selection circuit
15
, the column address selection circuit
17
, the column direction first program circuit
19
, the row direction second program circuit
21
, the differential sense amplifier circuit
23
, the comparison reference voltage generation circuit
27
, and the data input/output switching circuit
29
.
The address decoder circuit
25
is connected to the row address selection circuit
15
and the column address selection circuit
17
.
The row address selection circuit
15
, the column direction first program circuit
19
, and the row direction second program circuit
21
are each connected to the memory matrix array
13
.
The data input/output switching circuit
29
is connected to the column address selection circuit
17
, and the column address selection circuit
17
is connected to the memory matrix array
13
and the differential sense amplifier circuit
23
. The comparison reference voltage generation circuit
27
is connected to the differential sense amplifier circuit
23
.
The program operation in a non-volatile semiconductor memory device of the past will be described in terms of FIG.
4
. An address signal
33
that is input to the non-volatile semiconductor memory device is input to the address decoder circuit
25
, and sent to the row address selection circuit
15
and the column address selection circuit
17
.
By means of the address signal
33
that is sent to the row address selection circuit
15
and the column address selection circuit
17
, the row address selection circuit
15
and the column address selection circuit
17
select a specific memory of the memory matrix array.
A data
31
that is input to the data input/output switching circuit
29
is sent from the data input/output switching circuit
29
to the column address selection circuit
17
by a control signal from the control circuit
11
, the data
31
being input to a specific memory of the memory matrix array that is selected by the row address selection circuit
15
and the column address selection circuit
17
.
Finally, by means of a control signal from the control circuit
11
, the column direction first program circuit
19
and row direction second program circuit
21
operate, data
31
being programmed into a specific memory of the memory matrix array
13
that is selected by the row address selection circuit
15
and the column address selection circuit
17
.
Next, the operation of data readout in a non-volatile semiconductor memory device of the past will be described using FIG.
4
. An address signal
33
which is input to the non-volatile semiconductor memory device is input to the address decoder circuit
25
, this being sent to the row address selection circuit
15
and the column address selection circuit
17
.
By means of the address signal
33
which is sent to the row address selection circuit
15
and the column address selection circuit
17
, the row address selection circuit
15
and the column address selection circuit
17
select a specific memory of the memory matrix array
13
.
The specific selected memory data of the memory matrix array
13
is sent to the differential sense amplifier circuit
23
via the column address selection circuit
17
.
The differential sense amplifier circuit
23
is implemented by a conventional differential amplifier that is used in a general non-volatile semiconductor memory device, a signal voltage that is input to the differential sense amplifier circuit
23
from the comparison reference voltage generation circuit
27
is compared with a memory threshold voltage, which is the memory data that is input from the column address selection circuit
17
, the result being sent to the input/output data switching circuit
29
.
The signal that is sent to the data input/output switching circuit
29
is output as data
31
by means of a control signal from the control circuit
11
.
Next,
FIG. 3
will be used to describe the relationship between the memory data threshold voltage and the signal voltage from the comparison reference voltage generation circuit
27
.
FIG. 3
is a graph which shows the time variation characteristics of the threshold voltage value for memory into which data is programmed.
Both the curve
41
which shows retention of the memory threshold voltage value (data retention) for programming, from the threshold value
45
when the memory is fabricated, in the enhancement direction (that is, with the enhancement direction being the direction in which the Vth of an N-channel memory cell is a positive value of 0 or greater, the condition in the enhancement direction from the threshold value at the time of memory fabrication being defined as the written condition) and the curve
43
which shows the time variations of the memory threshold voltage value for programming, from the threshold value
45
when the memory is fabricated, in the depression direction (that is with the depression direction being the direction in which the Vth of an N-channel memory cell is a negative value of 0 or less, the condition in the depression direction from the threshold value at the time of memory fabrication being defined as the erase condition), approach the threshold voltage value
45
of the memory when fabricated.
In general, the comparison reference voltage value which is the signal voltage from the comparison reference voltage generation circuit
27
is designed to be the same as threshold voltage value
45
of the memory when it is fabricated. The threshold value at the time the memory is fabricated indicates the threshold value Vth (initial Vt) of a memory cell after the completion of the fabrication process and immediately before the first programming of the memory cell.
The differential sense amplifier circuit
23
of
FIG. 4
makes a comparison between the threshold voltage value
45
of the memory at the time of fabrication of the memory, which is the same value as the comparison reference voltage value shown in
FIG. 3
with the voltage value difference
47
of the memory threshold voltage value
41
of memory programmed in the enhancement direction, or a comparison between the threshold voltage value
45
of the memory at the time of fabrication of the memory, which is the same as the comparison reference voltage value, with the voltage value difference
49
of the memory threshold voltage value
45
of memory programmed in the depression direction, the results thereof being output to the data input/output switching circuit
29
of FIG.
4
.
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