Static information storage and retrieval – Addressing
Patent
1990-07-27
1992-02-04
Fears, Terrell W.
Static information storage and retrieval
Addressing
36523008, 365201, G11C 1300
Patent
active
050864130
ABSTRACT:
An EEPROM device comprises a memory cell array having a plurality of non-volatile memory cells respectively disposed at locations defined by word lines and bit lines and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which the row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate the other word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carries out the erase and write-in operations on a plurality of the non-volatile memory cells coupled to the word lines to be activated in the testing mode of operation.
REFERENCES:
patent: 5036491 (1991-07-01), Yamaguchi
Funahashi Norio
Tsuboi Toshihide
Fears Terrell W.
NEC Corporation
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