Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-18
2002-02-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S189060, C365S189090
Reexamination Certificate
active
06349060
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically, to an improvement of a sense amplifier of a flash memory.
2. Description of the Background Art
In a flash memory, the threshold voltage of a memory cell is made low or high by the program operation or an erase operation so as to distinguish between data “0” and data “1.” In a DINOR (DIvided NOR) type flash memory under development, the state of low threshold voltage is defined as a programmed state “0,” and the state of high threshold voltage is defined as an erased state “1.” To program data, high voltage pulses need to be applied repeatedly to a memory cell until the threshold voltage of the memory cell becomes lower than a prescribed voltage (program verify voltage PV). In addition, to erase data, high voltage pulses need to be applied repeatedly to the memory cell until the threshold voltage of the memory cell becomes higher than a prescribed voltage (erase verify voltage EV). Thus, when programming and erasing data, a verify operation must be performed for determining whether the threshold voltage of the memory cell has reached the prescribed voltage or not. The verify operation is performed using a sense amplifier for performing a normal read (“read” for short) operation in a similar manner.
FIG. 10
is a circuit diagram representing an arrangement of a conventional sense amplifier. As shown in
FIG. 10
, a sense amplifier
1
includes a verifying P-channel MOS transistor
2
, a normal-read P-channel MOS transistor
3
, an inverter
202
, an N-channel MOS transistor
203
, an inverter
204
, and a switch
207
. Switch
207
selects transistor
2
during the verify operation and selects transistor
3
during the normal read operation. Inverter
202
compares a memory cell current Icell that flows through a non-volatile memory cell
10
with a sense amplifier load current I
2
or a sense amplifier load current I
3
. As a result, sense amplifier
1
can determine the state of memory cell
10
.
During the verify operation and the normal read operation, the voltage of a source line SL attains a ground voltage, and the voltage of a word line WL attains a power-supply voltage Vcc. Thus, memory cell current Icell flows to memory cell
10
.
During the verify operation, transistor
2
supplies sense amplifier load current I
2
which is m times a constant current I
1
. Constant current I
1
is generated by a constant-current source
6
. Constant-current source
6
includes an N-channel MOS transistor
7
and a P-channel MOS transistor
8
. Transistor
7
has a constant reference voltage VREF applied at a gate so that it can supply constant current I
1
that is independent of power-supply voltage Vcc. Transistor
2
and transistor
8
together form a current mirror circuit. The size of transistor
2
is m (mirror coefficient) times that of transistor
8
. Thus, transistor
2
is capable of supplying sense amplifier load current
12
which is m times constant current I
1
.
On the other hand, during the normal read operation, transistor
3
supplies sense amplifier load current I
3
. Transistor
3
is independent from constant-current source
6
, and has a ground voltage applied to a gate so that transistor
3
can supply sense amplifier load current I
3
that is dependent on power-supply voltage Vcc.
FIG. 11
is a graph showing the relations of the voltage of the word line to the sense amplifier load current and the memory cell current.
During a program verify operation for verifying whether memory cell
10
has been programmed or not, a program verify voltage PV is applied to a word line WL, and program pulses are continually applied to memory cell
10
until a memory cell current Icell
0
that is to flow through memory cell
10
when data is “0” becomes greater than sense amplifier load current I
2
.
On the other hand, during an erase verify operation for verifying whether memory cell
10
has been erased or not, an erase verify voltage EV is applied to word line VL, and erase pulses are continually applied to memory cell
10
until a memory cell current Icell
1
that is to flow through memory cell
10
when data is “1” becomes smaller than sense amplifier load current I
2
.
From memory cell
10
in the programmed state (data “0”) or in the erased state (data “1”) thus formed, data “0” or data “1” is read using transistor
3
of sense amplifier
1
.
A normal-read sense amplifier load current I
3
depends on power-supply voltage Vcc, and becomes greater as power-supply voltage Vcc becomes higher as shown in FIG.
11
. Power-supply voltage Vcc fluctuates between a Vcc upper limit and a Vcc lower limit shown in FIG.
11
.
When memory cell
10
is in the programmed state, or when data “0” is stored in memory cell
10
, memory cell current Icell
0
is greater than normal-read sense amplifier load current
13
. As a result, sense amplifier
1
outputs an H (logic high) level signal.
On the other hand, when memory cell
10
is in the erased state, or when data “1” is stored in memory cell
10
, memory cell current Icell
1
becomes smaller than normal-read sense amplifier load current I
3
. As a result, sense amplifier
1
outputs an L (logic low) level signal.
FIG. 11
shows a read margin &Dgr;Ia at the Vcc lower limit and a read margin &Dgr;Ib at the Vcc upper limit. The smaller the fluctuation range of power-supply voltage Vcc, the greater read margins &Dgr;Ia and &Dgr;Ib become, whereby a stable read operation becomes possible.
The conventional sense amplifier, however, has such problems as described below.
One problem is that read margin &Dgr;Ia at the Vcc lower limit becomes smaller as the temperature gets lower.
FIG. 12
is a graph of a vicinity XII of the Vcc lower limit in
FIG. 11
shown enlarged. In
FIG. 12
, memory cell currents Icell
0
and normal-read sense amplifier load currents I
3
at a low temperature LT, a room temperature RT, and a high temperature HT (LT<RT<HT) are respectively shown. As shown in
FIG. 12
, memory cell current Icell
0
at the Vcc lower limit becomes smaller as the temperature gets lower. On the contrary, normal-read sense amplifier load current I
3
at the Vcc lower limit becomes greater as the temperature gets lower. Thus, read margin &Dgr;Ia at the Vcc lower limit becomes smaller as the temperature gets lower. In
FIG. 12
, the read margin at room temperature is denoted by &Dgr;Ia@RT, the read margin at a high temperature is denoted by &Dgr;Ia@HT, and the read margin at a low temperature is denoted by &Dgr;Ia@LT.
Another problem is that read margin &Dgr;Ia at the Vcc lower limit varies according to the variation of the process. As shown in
FIG. 10
, N-channel MOS transistor
7
generates constant current I
1
according to reference voltage VREF, and this current I
1
becomes smaller as a threshold voltage Vthn of transistor
7
gets higher. Thus, the verifying sense amplifier load current I
2
also becomes smaller as threshold voltage Vthn of transistor
7
gets higher.
FIG. 13
is a graph of the vicinity XII of the Vcc lower limit in
FIG. 11
shown enlarged. In
FIG. 13
, memory cell currents Icell
0
and verifying sense amplifier load currents I
2
at a low threshold voltage LVthn, a standard threshold voltage MVthn, and a high threshold voltage HVthn are respectively shown. At the Vcc lower limit, memory cell current Icell
0
and verifying sense amplifier load current I
2
become smaller as threshold voltage Vthn gets higher. Consequently, sense amplifier
1
might determine that the programming is completed even when memory cell current Icell
0
is small during the verify operation. Thus, read margin &Dgr;Ia at the Vcc lower limit becomes smaller as threshold voltage Vthn of transistor
7
becomes higher. In
FIG. 13
, the read margin at a low threshold voltage is denoted by &Dgr;Ia@LVthn, the read margin at a standard threshold voltage is denoted by &Dgr;Ia@MVthn, and the read margin at a high threshold voltage is denoted by &Dgr;Ia@HVthn.
Lam David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
LandOfFree
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