Non-volatile semiconductor memory device having a floating gate

Details Non-volatile semiconductor memory device having a floating gate Non-volatile semiconductor memory device having a floating gate

1996-10-24

1999-02-23

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518502, 36518506, 36518513, 36518518, 36518523, 36518525, 36518528, 365175, G11C 1602

Patent

active

058751270

ABSTRACT:
A memory array circuit has a matrix of column lines and row lines. A plurality of non-volatile storage capacitors, each having a floating gate for the storage of charges, are arranged in the matrix. Each storage capacitor has a data node and a voltage node, with a floating gate therebetween. Each of the plurality of non-volatile storage capacitors has an associated column line and an associated row line, with the voltage node connected to the associated row line. A diode connects the data node of a storage capacitor to its associated column line. A first decoder decodes a first address signal and selects one of the column lines. A second decoder decodes a second address signal, and generates a row output signal, with each row output signal of the second decoder having a corresponding row line. A plurality of voltage control circuits is provided with each voltage control circuit receiving one of the plurality of row output signals, and for applying a control signal to a corresponding row line, in response to a data read signal, a data write to one state signal or a data write to another state signal.

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patent: 4920513 (1990-04-01), Takeshita et al.
patent: 5361225 (1994-11-01), Ozawa
patent: 5379250 (1995-01-01), Harshfield
"Pinch Load Resistors Shrink Bipolar Memory Cells" by S.K. Wiedmann, Electronics, Mar. 7, 1974, pp. 130-133.
Intuitive IC Electronics by Thomas M. Frederiksen, McGraw-Hill Inc., 1989, pp. 193-194.

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