Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-13
2003-05-20
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185220, C365S185290
Reexamination Certificate
active
06567312
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims priority of Japanese Patent Application No. 2000-141072, filed, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for improving data holding of a non-volatile memory such as EEPROM (Electrical Erasable and Programmable Read Only Memory) and flash memory (an EEPROM capable of simultaneously erasing plural memory data in a memory cell block by one action). In more detail, the present invention relates to improvement of technique for making data reading characteristic more reliable by prohibiting memory data from easily deteriorating once after the data is stored into EEPROM memory cell, e.g., flash memory cell.
2. Discussion of the Related Art
A memory cell used in the non-volatile memory such as EEPROM and flash memory has generally been formed, according to the related art, with a double-gate structure including a floating gate electrode and a control gate electrode, provided in the laminating method holding a thin insulation film between these gate electrodes. However, recently the complicated manufacturing process of such double-gate structure distinctively impedes ultra-micro-miniaturization and attention is now paid to the new technique for realizing single gate structure as the gate structure.
In the case of such single gate type non-volatile memory, a material that can store charges, for example, a material of nitride film group is employed as a gate insulation film covered between a silicon substrate and a gate electrode and thereby charges may be stored by seizing the charges with the gate insulation film that can store charges in place of using a floating gate. As an example of a single gate type non-volatile semiconductor memory, a SONOS type memory has been proposed. This SONOS type memory has the laminated structure of silicon oxide film (SiO), silicon nitride film (SiN) and silicon oxide film (SiO) as a structure of gate insulation film and data recording can be realized by inputting or outputting the charges to or from the silicon nitride film (SiN). (The silicon oxide film (SiO) nearer to the silicon substrate is called the first gate oxide film and that nearer to the gate electrode is called the second gate oxide film.)
For such SONOS type memory cell, a cell layout in which the source and drain are connected in parallel is generally employed. In this layout, the sources and drains of a plurality of adjacent memory cells are connected in parallel to form the columns and a column is defined as a bit line. The bit line is connected to a sense amplifier via the selection gate. The gates of the adjacent memory cells in the column direction are coupled with a single wire as the word line.
Operations of the non-volatile semiconductor memory of such SONOS type memory cell are as follows.
[Data Write Operation]
Data write operation is performed by applying the write potential Vdp (about 5V) to the bit line connected to the drain of the selected cell, giving 0V to the bit line connected to the source and applying a word line Vwp (about 10V) to the word line. In this case, the bit line and word line of non-selected cell are floated to avoid the data writing. When the data write operation is performed as explained above, hot electrons are generated at the area near the drain in the selected cell. The hot electrons are trapped into the nitride film near to the drain, exceeding the barrier of the first gate oxide film. Thereby, a threshold voltage of the selected cell shifts in the positive direction. This condition is defined as “0”.
[Data Erase Operation]
The data erase operation is performed for all memory cells of the selected block by applying Vwe (about −3V) to all word lines of the selected block and setting all bit lines to Vbe (about 7V). Thereby, electrons trapped in the nitride film are removed and the threshold voltage is shifted in the negative direction. This condition is defined as “1”.
[Data Read Operation]
The data read operation is performed by applying Vwr (about 4V) to the word line connected to the selected memory cell, applying a read potential Vbr (about 1V) to the bit line connected to the drain and giving 0V to the bit line connected to the source. However, the relationship between the drain and source during the read operation is inverted from the relationship in the data write operation, because electrons are trapped at the area near the diffused layer defined as the drain at the time of data write operation. Namely, a larger shift of threshold value can be obtained when the drain and source are inverted. Data read is determined with the absolute value of a current flowing into the selected memory cell.
[Data Verifying Operation]
In the case of data verifying operation, after completion of the write operation explained above, the verifying operation is performed to confirm whether write operation is sufficient or not. If write operation is insufficient, re-writing is performed to such cell. The verifying operation and write operation are repeated until all data are written. In the case of erasing the verifying operation, the verifying operation is performed after the erase operation explained above. If erase is insufficient, the erase operation is executed again. These operations are performed until the erase operation is conducted sufficiently.
The SONOS type memory cell has a characteristic, unlike the floating gate type memory cell, to trap the electrons to the insulation film. Density of trapped charges is approximated as about 2.0×10
12
cm
−2
to 1.0×10
13
cm
−2
. This density is near to the interface level density at the interface of the substrate and first oxide film when the memory cell is deteriorated. Therefore, density of trap site in the SONOS type memory cell or at the interface with the substrate can be compared with the trap site in the nitride film and therefore gives a large influence on the transistor characteristic. When the write/erase characteristic explained above is repeated, the first gate oxide film and interface are deteriorated and an extra trap site is increased. Namely, here rises a problem that while operation is continued, the memory cell characteristic, particularly the read characteristic is deviated from the initial characteristic.
This problem is not limited to the SONOS type memory cell but is true to all memory cells in which an insulation film that can easily capture the electrons more than the silicon oxide film is formed on a gate oxide film and this insulation film is used as the electron trap.
SUMMARY OF THE INVENTION
As explained above, in the SONOS type non-volatile memory cell of the related art and also in the memory cell of the type to trap charges with a gate insulation film, extra trap site increases at the first gate oxide film and the interface thereof, and the memory cell read characteristic is thereby extremely deteriorated. Such problems have been appeared.
Referring to
FIG. 1
FIG. 1
is a graph (No. 1) showing the read characteristic of the SONOS type non-volatile memory of the related art, indicating, on the same graph for the purpose of comparison, the characteristic (white square points) in the condition to start the application (initial condition) and the operation (“cycling” operation) to repeat the data write and erase operations for 10,000 times (black circular points) wherein the gate voltage (vg) is plotted on the horizontal axis and the drain current (Id) on the vertical axis. As will be apparent from
FIG. 1
, in the initial condition, when the gate voltage (Vg) is raised, the drain current (Id) responds sharply at a certain area and the response characteristic called “Cut-Off characteristic” can be assumed. However, after the cyclic operations of 10,000 times, such sharp cut-off characteristic is clearly deteriorated. Namely, after the cyclic operations of 10,000 times, the drain current (Id) only rises gradually and does not rise
Kojima Hideyuki
Mawatari Hiroshi
Torii Satoshi
Arent Fox Kintner Plotkin & Kahn
Ho Hoai
LandOfFree
Non-volatile semiconductor memory device having a charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory device having a charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device having a charge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3076006