Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-08-20
2004-03-23
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185290, C365S185300
Reexamination Certificate
active
06711061
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an inflicting voltage controlling method employed for the erasing processing for a non-volatile semiconductor memory device and a non-volatile semiconductor memory device that employs the method.
BACKGROUND OF THE INVENTION
A floating gate electrode type non-volatile memory element (hereinafter “cell”) stores information according to a different cell characteristic decided by the number of electrons accumulated in their floating gate electrodes, i.e. a difference between threshold voltage values of the cells. Hereinafter, a processing for increasing a threshold voltage is defined as “writing” and a processing for decreasing the threshold voltage to a predetermined value is defined as “erasing”. Accordingly, the processing for increasing the threshold voltage is defined as “erasing” and the processing for decreasing the threshold voltage to a predetermined value is defined as “write”.
FIG. 2
shows a graph for denoting distribution of threshold voltages of the cells of a general non-volatile semiconductor memory device in which each memory array is composed of a plurality of cells. A writing level is decided by the writing lower limit value V
pmin
and the threshold voltages are distributed as denoted by A. In an erasing processing, a predetermined voltage is inflicted to the cell group set in the state of distribution A so as to lower each respective threshold voltage. Usually, because the erasing characteristic is varied, when a processing for lowering a threshold voltage is executed simply as such, the threshold voltages are distributed in a wide-base shape as denoted by B. A cell group (dark portion) of which the threshold voltage is under the erasing lower limit value V
emin
(over erasing level) becomes a source of leak current, thereby information cannot be read therefore correctly. In order to prevent such a problem, therefore, the data in each cell on the over erasing level is rewritten so that the erasing level is adjusted to a predetermined erasing level distribution C (within a range between the erasing lower limit value V
emin
and the erasing upper limit value V
emax
).
Conventionally, there have been two methods for lowering threshold voltages: one is a method for managing a plurality of word lines collectively (hereinafter, to be described as the “block processing”) and the other is a method for managing the threshold of each cell in units of a word line (hereinafter, to be described as the “sector processing”). In the case of the block processing, a target block including a plurality of word lines is selected according to the information stored in the corresponding register. For example, a well potential is used as a block selecting signal and a negative voltage is inflicted to all the word lines in the selected block. The charge accumulated in a cell is discharged with an electric field generated by the negative voltage and a positive potential inflicted to the well. Then, the threshold voltage of each cell is checked. When there is a cell of which threshold voltage is not under the reference value, a negative voltage is inflicted again to all the word lines in the block. These processings are repeated. When the threshold voltages of all the cells in the block become lower than the reference value, the system goes to the next block so as to execute another erasing processing. Because the block processing can process many cells at a time, it takes less time for lowering each threshold voltage.
The sector processing manages the threshold voltage of each cell in units of a word line. After a negative voltage is inflicted to a word line, the threshold voltage of the cell connected to the word line is checked. When a cell of which threshold voltage is not under the reference value is detected, a negative voltage is inflicted again to the word line. When the threshold voltage of every cell connected to the word line goes under the reference value, the system goes to the next word line. In the case of this method, a negative voltage for lowering each threshold voltage is inflicted to just the number of cells connected to a word line. Statically, the fewer the word lines, the narrower the threshold voltage distribution after a processing can be than that of the block erasing processing. On the other hand, when compared with the block processing, the processing time becomes longer unavoidably.
Furthermore, after an erasing processing executed for a cell, another processing is done so as to increase the threshold voltage of the cell, which has been decreased excessively. This processing is referred to as “rewriting”. In any of the block processing and the sector processing described above, it cannot be avoided that some cells go into such the over erased state after an erasing processing. This is why such the rewriting is done as “a weak writing” for the cells that are in the over erased state. Because the writing characteristic is varied just like the erasing characteristic, the threshold voltages must be controlled precisely so that they are settled on a predetermined erasing level shown in FIG.
2
.
There is a well-known method for inflicting a voltage to cells so as to write data therein accurately. According to the method, a pulse voltage inflicted to both drain and gate of each cell is increased by increments through the hot electron injection method. The threshold voltages of cells in which data can be written fast can be controlled easily and settled on a predetermined erasing level at the initial infliction of a low voltage. On the other hand, the threshold voltages of cells in which data is written slowly at a low voltage are controlled so as to be settled quickly on the predetermined erasing level by a high voltage inflicted in the latter half. Such the writing voltage inflicting method is disclosed in U.S. Pat. No. 5,642,309 and JP-A-Nos. 228784/1998.
In the case of the block processing, since there are many target cells, the threshold voltages are distributed widely and the number of cells to be set in the over erased state increases after each processing, suffering from the increase in rewriting processing time. In the case of the sector processing, a processing for inflicting a voltage used to lower a threshold voltage must be executed for each of word lines, causing the voltage inflicting time to increase. In order to reduce the whole erasing processing time, it is required to reduce both processing times for lowering each threshold voltage and rewriting data. In principle, however, it has been difficult for any of the conventional block and sector processings to reduce both of such the processing times.
Under such circumstances, it is an object to provide a method that enables rewriting to be done so that threshold voltages of memory cells are settled easily on a predetermined level. In order to achieve the above object, the writing pulse voltage is increased by increments for rewriting. And, a minimum level a maximum value, an increment value, and a pulse time should be set properly for each voltage to be inflicted. When there is an excessively high stress recognized on the pulse voltage value, (for example, when the start voltage is excessively high), in which cells data can be rewritten fast might exceed the upper limit value of the erasing level. When the start voltage is excessively low or when the maximum inflicting voltage is excessively low, the rewriting is done slowly which causes the processing time to increase. Setting pulses of the voltage to be inflicted is also an important item to solve the above conventional problems.
SUMMARY OF THE INVENTION
Word lines in a selected block, when their threshold voltages are within a proper range in an erasing processing, are excluded from an additional erasing processing respectively. Whether to select a word line for such an additional erasing processing is done by controlling a latch circuit connected to the word line according to the information of processing end stored in a register. The subject memory is prevented from an increase of the occu
Matsuzaki Nozomu
Shiba Kazuyoshi
Shinagawa Yutaka
Tanaka Toshihiro
Taniguchi Yasuhiro
Hitachi , Ltd.
Phan Trong
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