Non-volatile semiconductor memory device erasing operation

Details Non-volatile semiconductor memory device erasing operation Non-volatile semiconductor memory device erasing operation

1989-07-06

1991-02-26

Hille, Rolf

Static information storage and retrieval

Magnetic bubbles

Guide structure

365185, 365218, H01L 2968, G11C 1134, G11C 700

Patent

active

049965719

ABSTRACT:
The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.

REFERENCES:
patent: 4742492 (1988-03-01), Smayling et al.
patent: 4797856 (1989-01-01), Lee et al.
Yaron et al., "A 16K E.sup.2 PROM Employing New Array Architecture and Designed-In Reliability Features", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 833-840.
Gee et al., "An Enhanced 16K E.sup.2 PROM", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 828-832.

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