Non-volatile semiconductor memory device detachable deterioratio

Details Non-volatile semiconductor memory device detachable deterioratio Non-volatile semiconductor memory device detachable deterioratio

1994-04-25

1995-09-12

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 365207, 365208, 36518901, G11C 1718

Patent

active

054503540

ABSTRACT:
A non-volatile semiconductor memory device capable of electrical programming including a plurality of memory cells, means for selecting at least one memory cell from the plurality of memory cells, mode setting means for setting one of a first read mode in which data written in the selected memory cell is read and a second read mode for detecting a change of the threshold voltage level of the selected memory cell, first comparing means for comparing a voltage signal read from the selected memory cell with at least a predetermined single first reference voltage level when the first read mode is set, first output means for producing a signal indicative of data written in the selected memory cell on the basis of the comparison in the first comparing means, second comparing means for comparing the cell voltage signal with at least a predetermined single second reference voltage level different from the first reference voltage level when the second read mode is set, and second output means for producing a signal indicative of a change of the threshold voltage of the selected memory cell on the basis of the comparison in the second comparing means.

REFERENCES:
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patent: 4964079 (1990-10-01), Devin
patent: 5012448 (1991-04-01), Matsuoka et al.
patent: 5043940 (1991-08-01), Harari
patent: 5297088 (1994-03-01), Yamaguchi
A 16Kb Electrically Erasable Nonvolatile Memory, Johnson, 1980 IEEE ISSCC Dig. Tech. Paper pp. 152-153, 271; 1980.
Analysis and Modeling of Floating-Gate EEPROM Cells, Kolodny et al., IEEE Trans. Electron Devices, Jun. 1986, ED-33, No. 6, pp. 835-844.
Semiconductor MOS Memory and Method of Using the Same, Nikkan Kogyo Newpapers Co., 1990, pp. 96-101.
A Novel Cell Structure Suitable For A 3 Volt Operation, Sector Erase Flash Memory, Onoda et al., IEDM 92, pp. 599-602, 1992.

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