Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-07
2004-09-07
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06788581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices providing reduced probabilities of erroneously reading data from memory cells.
2. Description of the Background Art
A non-volatile semiconductor memory device having a memory cell in the form of a transistor having a threshold voltage varying as a stored data level varies has its data read via a so-called discharging read circuit, a circuit through current detection, and the like.
For example, when the discharging read circuit is used, a memory cell has its content read, as follows: the time when a memory cell hardly passes an electric current as its content is read is the time when a low level is read. By contrast, the time when a high level is read is the time when a memory cell capable of passing an electric current larger than that of a saturation range of a transistor operating as an electric current source connected to a node subjected to a decision between the high and low levels (note that hereinafter the transistor will be referred to as a “current source transistor”), has its content read. The discharging read circuit can thus determine whether a memory cell has the voltage of the high level or that of the low level.
A conventional discharging read circuit, however, has used a current source transistor which has not necessarily been given consideration to operate in an appropriate range, so that data may be read erroneously. More specifically, when the low level is read by the conventional discharging read circuit, a data line may have noise thereon or charge-share may be introduced so that the node subjected to a decision between the high and low levels may have a voltage drop to permit the current source transistor to supply an electric current smaller than the transistor's saturation current, when the current source transistor operates in a linear range and data may thus be read erroneously.
FIG. 11
shows a configuration of a conventional discharging read circuit. As shown in
FIG. 11
, the conventional discharging read circuit, i.e., a non-volatile semiconductor memory device
106
includes a memory cell array
1
having a plurality of memory cells (not shown), an n-channel MOS transistor NM
1
operative in a data read in response to a clock signal CNT to electrically couple nodes N
3
and N
4
together, a p-channel MOS transistor Tr
15
provided between a power supply voltage Vcc and n-channel MOS transistor NM
1
and acting as a current source transistor, and an inversion circuit
3
having as an input a connection node connecting p- and n-channel MOS transistors Tr
15
and NM
1
together to receive, invert and output a voltage level of an input signal.
Memory cell array
1
includes a word line and a bit line, and a word line decoder and a bit line decoder (not shown) for selecting a single memory cell from the plurality of memory cells. By way example, p-channel MOS transistor Tr
15
has a threshold voltage of 0.6V and inversion circuit
3
has a threshold voltage of 1.5V for the sake of illustration.
N-channel MOS transistor NM
1
is connected to memory cell array
1
through a node N
4
. P-channel MOS transistor Tr
15
, constantly supplying a current, typically has its gate connected to a ground voltage GND.
Node N
3
is designed to be sufficiently short to be hardly affected by noise. By contrast, in general, node N
4
, providing a connection between n-channel MOS transistor NM
1
and memory cell array
1
, would inevitably be sufficiently longer than node N
3
. In nodes N
3
and N
4
there exist parasitic capacitances C
2
and C
1
, respectively, and there exist a relationship C
1
>C
2
. Power supply voltage Vcc is set to be 3V for the sake of illustration.
FIG. 12
represents a characteristics curve T
1
a
representing characteristics of p-channel MOS transistor Tr
15
for a value k of 1.2 &mgr;A/V
2
. Value k indicates how readily/hardly p-channel MOS transistor Tr
15
passes an electric current. In the figure, the vertical axis represents the electric current passed by p-channel MOS transistor Tr
15
and the horizontal axis represents the voltage of node N
3
.
It is understood from the
FIG. 12
curve T
1
a
that p-channel MOS transistor Tr
15
in a saturation range passes a current (a saturation current) having a value of 7.2 &mgr;A. Furthermore, for curve T
1
a
, p-channel MOS transistor Tr
15
for a voltage smaller than 0.6V operates in the saturation range and for a voltage larger than 0.6V operates in a linear range.
Reference will now be made to
FIGS. 11 and 12
to describe how non-volatile semiconductor memory device
106
operates when the high and low levels are read therefrom. When data is not read, node N
3
has a voltage of 3V.
In reading data of the high level, a memory cell selected from the plurality of memory cells of memory cell array
1
(hereinafter referred to as a selected memory cell) is by way example capable of passing a maximal current of 10 &mgr;A for the sake of illustration. Whether an output OUT is the high or low level is determined as follows: it has the high level when node N
3
has a voltage smaller than the threshold voltage of inversion circuit
3
, and it has the low level when node N
3
has a voltage larger than the threshold voltage of inversion circuit
3
.
In a data read, with p-channel MOS transistor Tr
15
having a saturation current of 7.2 &mgr;A, a selected memory cell can pass a larger amount of current than p-channel MOS transistor Tr
15
. As such, node N
3
subjected to a decision between the high and low levels has a voltage drop substantially to 0V.
Thus the node N
3
voltage is smaller than the inversion circuit's threshold voltage of 1.5V and output OUT is set to be the high level.
Should node N
4
have noise thereon or between nodes N
3
and N
4
charge-share be introduced and node N
3
have a voltage dropping to be lower than the threshold voltage of 1.5V of inversion circuit
3
, output OUT is set to be the high level and data is not read erroneously.
When the low level is read, a selected memory cell hardly passes a current, for the sake of illustration. By way of example, the selected memory cell provides a leak current of 0.1 &mgr;A.
In a data read, the selected memory cell can only pass a current of 0.1 &mgr;A. As such, node N
3
subjected to a decision between the high and low levels hardly has a voltage drop. It substantially has a voltage of 3V.
If in this state for example node N
4
has noise thereon or between nodes N
3
and N
4
charge-share is introduced and as a result node N
3
has a voltage drop and instantly a current between 6 &mgr;A and 7.2 &mgr;A is passed allowing p-channel MOS transistor Tr
15
to operate in the linear range, then node N
3
has a voltage reduced to be smaller than the threshold voltage of 1.5V of inversion circuit
3
and despite that low-level data should be read, output OUT is set to be the high level and data would be read erroneously.
Thus in the conventional non-volatile semiconductor memory device a current source transistor's appropriate gate voltage level has not particularly been considered. As a result, when a node subjected to a decision between the high and low levels has a voltage falling within a range of no more than a threshold voltage, the current source transistor tends to operate in a linear range. As such, in reading the low level when charge-share, noise on a data line, or the like causes an electric current smaller than the current source transistor's saturation current to flow, a node subjected to a decision with respect to voltage can have a voltage of no more than the threshold voltage. Because of such a phenomenon, the conventional non-volatile semiconductor memory device has a high possibility that data is read from a memory cell erroneously.
SUMMARY OF THE INVENTION
The present invention contemplates a nonvolatile semiconductor memory device preventing erroneous reading of data in reading the low level when noise on a data line, charge-share, or the like has an effect to allow a curr
Le Thong
McDermott Will & Emery LLP
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