Non-volatile semiconductor memory device conducting data...

Details Non-volatile semiconductor memory device conducting data... Non-volatile semiconductor memory device conducting data...

2001-09-24

2003-03-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189040, C365S189011

Reexamination Certificate

active

06529418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device conducting a data write or data erase operation based on a prescribed unit region.
2. Description of the Background Art
A flash memory is a typical example of electrically erasable non-volatile memories.
FIG. 22
is a conceptual diagram showing the memory cell structure of the flash memory.
Referring to
FIG. 22
, a memory cell MC of the flash memory includes a source
2
and a drain
3
. The source
2
and the drain
3
are n
+
regions, and are formed at a p-type substrate
1
. The memory cell MC further includes a floating gate
4
and a control gate
5
. The floating gate
4
and the control gate
5
are deposited on the p-type substrate
1
so as to be insulated by an insulating film
6
. In particular, an insulating film between the floating gate
4
and the control gate
5
is also referred to as an inter-poly insulating film
6
a
, and an insulating film between the floating gate
4
and the p-type substrate
1
is also referred to as a tunnel insulating film
6
b
. Thus, the memory cell MC corresponds to an n-channel field effect transistor formed on the p-type substrate
1
.
The control gate
5
is coupled to a word line WL for selecting the memory cell MC. The source
2
and the drain
3
are respectively coupled to a source line SL and a bit line BL.
In the initial state, i.e., in the data erase state, electrons
7
are drawn out of the floating gate
4
of the memory cell MC.
In contrast, a data write operation to the memory cell MC is conducted by injection of the electrons
7
into the floating gate
4
by Fowler-Nordheim tunneling. The memory cell MC having the electrons
7
injected into the floating gate
4
, i.e., in the data write state, has a higher threshold voltage than in the data erase state.
Accordingly, selectively writing the data to a part of the memory cell group in the data erase state enables the storage data to be read according to the threshold voltage value of each memory cell MC. The storage data is read in the following manner: with the bit line being precharged, a fixed voltage is applied to the word line WL connected to the control gate so as to cause memory discharge for a prescribed period, and then a potential on the bit line is detected.
FIGS. 23A
to
23
C are conceptual diagrams illustrating data erase, write and read operations of the flash memory.
Note that
FIGS. 23A
to
23
C illustrate the respective operations to and from a memory cell group arranged in two rows by two columns. Word lines WL
1
and WL
2
are provided corresponding to the respective memory cell rows, and bit lines BL
1
and BL
2
are provided corresponding to the respective memory cell columns. The source line SL is provided in common to the memory cells.
In the specification, a prescribed unit region that is subjected to a single data write operation or data erase operation is referred to as a “sector”. A single sector herein corresponds to a memory cell group selected by a single word line.
Referring to
FIG. 23A
, the data erase operation is conducted on a sector-by-sector basis. The word line WL
1
of the selected sector is set to a negative high voltage Vnn, as well as the source line SL and the bit lines BL
1
, BL
2
are grounded. The word line WL
2
of the non-selected sector is grounded.
As a result, the negative high voltage Vnn and the ground voltage Vss are respectively applied to the control gates and sources of the memory cells of the selected sector. Thus, in each memory cell of the selected sector, electrons are drawn out of the floating gate by the Fowler-Nordheim tunneling, whereby the data is erased.
Referring to
FIG. 23B
, the data write operation is conducted on a sector-by-sector basis. The word line WL
1
of the selected sector is set to a high voltage Vpp with the source line SL being opened.
According to the write data, a write inhibit voltage Vdi and a ground voltage Vss are selectively applied to each bit line. In a memory cell receiving the high voltage Vpp and the ground voltage Vss at its control gate and drain through the word line and the bit line, respectively, electrons are injected into the floating gate by the Fowler-Nordheim tunneling, whereby the data is written thereto. However, the data is not written to a memory cell receiving the high voltage Vpp and the write inhibit voltage Vdi at its control gate and drain, respectively.
In order to prevent drain disturb, a voltage Vwi having about the same value as that of the write inhibit voltage Vdi is applied to the word line WL
2
of the non-selected sector.
Thus, controlling the respective drain voltages of the plurality of memory cells coupled to the same word line WL through the bit lines allows for the selective data write operation.
For example, in
FIG. 23B
, the word line WL
1
is selected to be driven to the high voltage Vpp. In response to this, the data is written to a memory cell MCa coupled to the bit line BL
1
of the ground voltage Vss. However, the data is not written to a memory cell MCb coupled to the bit line BL
2
of the write inhibit voltage Vdi.
Thus, by first erasing the data from each memory cell MC and then selectively writing the data thereto, only the threshold voltage of the written memory cell is increased.
Referring to
FIG. 23C
, in the data read operation, each bit line is precharged to a prescribed voltage Vdr. Then, a prescribed data read voltage Vwr is applied to the selected word line for a prescribed period. Thus, the control gates of the corresponding memory cells are set to the prescribed voltage Vwr. The word line WL
2
of the non-selected sector is retained at the ground voltage Vss.
By appropriately setting the voltages Vwr, Vdr in view of the threshold voltage of the written memory cell, the charges precharged in the written memory cell are stored therein. However, the charges precharged in the non-written memory cell are discharged therefrom. Accordingly, the data can be read by detecting the amount of charges remaining on the bit line.
Thus, depending on whether the electrons are injected into the floating gate or not, the data can be written to each memory cell MC in a non-volatile manner as well as the storage data thereof can be read.
FIG. 24
is a conceptual diagram showing the threshold voltage distribution of the memory cells of the flash memory.
Referring to
FIG. 24
, a memory cell in the data write state, i.e., having the storage data level of “0”, has a higher threshold voltage than that of a memory cell in the data erase state, i.e., having the storage data level of “1”.
In each state, the memory cell group has a variation in threshold voltage distribution. Therefore, in view of this variation, a data read level Vtr is set so that the respective threshold voltages can be distinguished from each other. Thus, the data can be read from the memory cell.
In other words, in the data read operation, prescribed applied voltages to the memory cells, i.e., Vwr and Vdr in
FIG. 23C
, are set so that a current flows through a transistor whose threshold voltage corresponds to the data read level Vtr.
Recently, so-called multi-level technology capable of writing a plurality of data levels to each memory cell has been used for reduced costs and increased capacity of the flash memory. For example, in a 2 bits/cell flash memory, two-bit information is stored in a single memory cell.
FIG. 25
is a conceptual diagram showing the threshold voltage distribution of the memory cells of the 2 bits/cell flash memory.
Referring to
FIG. 25
, in the 2 bits/cell flash memory, three data write states L1, L2 and L3 are defined in addition to the data erase state corresponding to the storage data level of“11”. For example, the data write states L1, L2 and L3 respectively correspond to the storage data levels of “00”, “01” and “10”.
Appropriately setting the data write conditions such as an applied voltage level in th

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