Non-volatile semiconductor memory device capable of reducing...

Details Non-volatile semiconductor memory device capable of reducing... Non-volatile semiconductor memory device capable of reducing...

2000-10-31

2002-08-13

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S189050, C365S189070

Reexamination Certificate

active

06434042

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-47958, filed on Nov. 1, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having page buffer circuits.
BACKGROUND OF THE INVENTION
Semiconductor memory devices for storing data are typically classified into volatile and non-volatile types. The volatile memory devices cannot hold data stored in their memory cells when their power supplies are shut down. However, the non-volatile memory devices retain their stored data even without power supplies. Therefore, the non-volatile memory devices are widely used in applications where the possibility of power supply interruption is present.
One type of nonvolatile memory devices includes an electrically erasable programmable read only memory (EEPROM) device, which is generally referred to as a flash EEPROM device. An EEPROM device is constructed on semiconductor substrate with N-type source/drain regions, a channel region between the source/drain regions, a floating gate for storing electrical charge, and flash EEPROM cells having a control gate located over the floating gate. Operation modes of a flash memory device are include programming, erasing, and reading.
Conventionally, in order to store data in a flash EEPROM, the cell is programmed. But programming is carried out after erasing the cell, to ensure no residual charges are stored in the floating gate from a previous operation.
An erase operation is achieved by applying 0V to the control gate, and a high voltage (e.g., 20V) to a semiconductor substrate (or a bulk). In this state, negative charges accumulated in a floating gate are discharged to the semiconductor substrate via a tunneling oxide layer by a mechanism called “F-N tunneling (Fowler-Nordheim tunneling)”. This makes an effective threshold voltage (Vth) of a flash memory cell transistor acquire a negative voltage. In erase operation, an EEROM cell stores logic “1” (or logic “0”). When a predetermined read voltage (Vread) is applied to the control gate during read operation (i.e., Vth<Vread), the cell transistor is at a conductive state (i.e., “ON”).
Programming a flash EEPROM cell is achieved by applying a high voltage (e.g., 18V) to a control gate, and 0V to a source, a drain, and a semiconductor substrate. In this state, negative voltages are accumulated in an effective threshold voltage of the flash EEPROM by F-N tunneling. This makes an effective threshold voltage (Vth) of a flash EEPROM cell transistor have a positive voltage. In program operation, the EEPROM cell stores logic “0” (or logic “1”). When a predetermined read voltage (Vread) is applied to the control gate during read operation (i.e., Vth>Vread), the cell transistor is at a nonconductive state (i.e., “OFF”).
Such program and read operations are disclosed in U.S. Pat. No. 5,841,721.
Reading the EEPROM cell is achieved by applying a read voltage to the control gate via a wordline, and by supplying load current to the drain region via a bitline. At this time, a source region is grounded. If an EEPROM cell is programmed, the EEPROM cell does not conduct cell current, and a voltage of a bitline connected thereto becomes higher than a predetermined voltage. If an EEPROM cell has not been programmed (or has been erased), the EEPROM cell will flow a large amount of cell current, and thus pull a voltage of a bitline down to a ground voltage. Thus, a bitline voltage (or current) is monitored to determine a programmed state (i.e., “1” or “0”) of the EEPROM cell.
Referring now to
FIG. 1
, a NAND-type flash memory device including EEPROM cells is described. A memory device shown in
FIG. 1
includes an array
10
having a plurality of memory cell strings
30
. Each of the strings
30
is composed of a plurality of EEPROM cell transistors Mj (j=0~5), which are serially connected between a source of a string transistor SST and a drain of a ground selection transistor GST. The drain of string transistor SST is connected to a corresponding bitline BLi (i=0~1023). The source of ground selection transistor GST is connected to a common source line CSL. A gate of the string selection transistor SST is coupled to a string selection line SSL, and a gate of the ground selection transistor GST is coupled to a ground selection line GSL. Control gates of the EEPROM cell transistors M
0
~M
15
are coupled to corresponding wordlines WL
0
~WL
15
, respectively. The lines SSL, WL
0
~WL
15
, and GSL are led from a row decoder circuit
20
.
A read operation is carried out using page buffers
40
is shown in FIG.
1
. Such page buffers are disclosed in U.S. Pat. No. 5,761,132.
Referring now to
FIG. 2
, a timing view is given to illustrate how the read operation is performed. When the read operation starts, signals SBL and DCB are activated, each with a low-to-high transition, as shown in FIG.
2
. Thus, NMOS transistors
42
and
43
of page buffers
40
are turned on, and sensing nodes S
0
are discharged to a logic low level (e.g., a ground voltage level). And, bitlines BL
0
-BL
1023
(each of which is connected to sensing nodes S
0
via depletion transistors
48
) are also discharged to a logic low level.
String and ground selection line signals SSL and GSL, and unselected wordlines (e.g., WL
1
~WL
15
) are driven with a predetermined voltage (Vr) for carrying out a read operation controlled by a row decoder circuit
20
. Signals Olatch and Osae, and a selection wordline (e.g., WL
0
) all retain a ground voltage level, and signal Oblsh retains a logic high level (e.g., a power supply voltage level). In this state, a node A
0
retains a logic high level (i.e., a power supply voltage level) via PMOS transistors
51
and
52
. The node A
0
is commonly coupled to gates of PMOS transistors
41
(serving as load transistors) which are coupled to bitlines BL
0
~BL
1023
, respectively.
With low-to-high transition of the signal Osae, a PMOS transistor
51
is turned off, while an NMOS transistor
54
is turned on. Thus, the node A
0
decreases to a specific voltage level (e.g., 1.2V) from a power supply voltage level, via NMOS transistors
53
and
54
. A reference voltage Vref of about 0.8V is applied to a gate of the transistors
53
, lightly conducting a PMOS transistor
41
of each page buffer
40
. Consequently, each of the bitlines BL
0
~BL
1023
receives load current which flows thereinto, via corresponding PMOS transistors
41
.
When load current is applied to each of the bitlines BL
0
~BL
1023
, a voltage induced to each bitline changes according to a state of a cell transistor. For example, when a selected flash EEPROM cell is programmed, load current is accumulated on a bitline, because a cell threshold voltage Vth is higher than a wordline voltage (e.g., 0V). Therefore, a bitline voltage is identical to, or higher than a predetermined voltage level (e.g., 0.9V). Thus, a depletion transistor
48
is shut off, and a sensing node S
0
rises up to near the power supply voltage. On the other hand, when a cell is erased, load current is discharged to a common source line CSL via a cell, because a threshold voltage Vth of the cell is lower than a wordline voltage. Therefore, both a bitline and a sensing node S
0
go to a ground voltage level.
When the signal Olatch then transitions from a low level to a high level, a node of each latch LT changes with a voltage level of the sensing node S
0
. In the former case, the node is grounded via the NMOS transistors
46
and
47
, because they are turned on. In the latter case, the node holds an initially set level, because the NMOS transistor
46
is turned off.
Referring to
FIG. 2
, time required in a read operation, i.e., read time T
1
is influenced by time T
2
required for setting a voltage of a node A
0
to a required voltage level. In other words, as time T
2
is large, it forces time T
1
to remain large.
Time T
2
is large because the node A
0
is commonly coupled to

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