Non-volatile semiconductor memory device capable of preventing e

Details Non-volatile semiconductor memory device capable of preventing e Non-volatile semiconductor memory device capable of preventing e

1995-04-19

1996-09-24

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518514, 36518529, 365218, G11C 1134

Patent

active

055597360

ABSTRACT:
After data is written into a desired memory cell of a memory cell array, a booster circuit verifies the threshold voltage of the memory cell in which data is written. An erase timing signal generation circuit connected to a control circuit generates a timing signal for a short period of time when a memory cell having a threshold voltage higher than the power supply voltage. An erasing voltage generation circuit applies a negative erasing voltage to the memory cell in which data is written for a short period of time according to the timing signal supplied from the erase timing signal generation circuit to slightly lower the threshold voltage of the memory cell so as to prevent the excessive writing.

REFERENCES:
Publication, "A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond", by K. Oyama et al., pp. 24.5.1-24.5.4, Dec. 2, 1990.

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