Non-volatile semiconductor memory device capable of high speed p

Details Non-volatile semiconductor memory device capable of high speed p Non-volatile semiconductor memory device capable of high speed p

1997-07-18

1998-10-06

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36518513, 36518524, G11C 1604

Patent

active

058187618

ABSTRACT:
To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

REFERENCES:
patent: 5218571 (1993-06-01), Norris
patent: 5303189 (1994-04-01), Devin et al.
patent: 5398203 (1995-03-01), Prickett, Jr.
patent: 5576990 (1996-11-01), Camerlenghi et al.
"Novel Electron Injection Method Using . . . with a P-Channel Cell", Ohnakado et al.., IEDM 95, pp. 279-282.
"A High Programming . . . DINOR Flash Memory", O. Sakamoto et al., 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 222-223.
"3.3V-Only 16 Mb DINOR Flash Memory", S. Kobayashi et al., 1995 IEEE International Solid-State Circuits Conference, pp. 122-123.

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