Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-08-17
2003-05-13
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185280
Reexamination Certificate
active
06563734
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device having electrically erasable, writable and readable functions. More particularly, the present invention relates to a non-volatile semiconductor memory device capable of executing these functions at the same time.
BACKGROUND OF THE INVENTION
In electrically batch-erasable, writable, and readable non-volatile semiconductor memory devices, erase and write operations require several hundred- to several hundred thousand-folds operation time relative to a read operation. Therefore, a single non-volatile semiconductor memory device can carry out neither a write operation nor a read operation during an erase operation and, can carry out neither an erase operation nor a read operation during a write operation.
Accordingly, in order to carry out erase, write and read operations simultaneously, a system such as electrical products need to have multiple non-volatile semiconductor memory devices so that while an erase or write operation is carried out with one non-volatile semiconductor memory device, a read operation with another non-volatile semiconductor memory device.
JP-A 7/281952 discloses a method of carrying out simultaneously two or more functions of erase, write, and read operations. A method using a latch circuit is described in
FIG. 7
as a Conventional Example 1, and a method using a selector circuit in
FIG. 8
as a Conventional Example 2. The prior art disclosed in JP-A 7/281952 will be illustrated hereinafter by referring to
FIGS. 7 and 8
.
FIG. 7
shows a block diagram representing a constitution of the Conventional Example 1. A non-volatile semiconductor memory device (IC)
1
comprises a control signal
2
entered from outside, data
3
, address
4
, and a power supply
5
. A command analyzing and status data generating part
6
analyzes a command entered as data
3
, and controls the whole of IC
1
.
The IC
1
further comprises an erase control part
7
and a write control part
8
. The erase control part
7
transmits a status signal
7
a
to communicate that the erase control part
7
is busy to the command analyzing and status data generating part
6
, a request signal
7
b
which is transmitted to the command analyzing and status data generating part
6
before the erase control part
7
uses a bus
9
(
9
a
~
9
h,
9
i
), and an acknowledge signal
7
c
to communicate that the bus
9
(
9
a
~
9
h,
9
i
) is able to be used to the erase control part
7
when the command analyzing and status data generating part
6
obtains the request signal
7
b.
The write control part
8
transmits a status signal
8
a
to communicate that the write control part
8
is busy to the command analyzing and status data generating part
6
, a request signal
8
b
which is transmitted to the command analyzing and status data generating part
6
before the write control part
8
uses a bus
9
(
9
a
~
9
h,
9
j
), and an acknowledge signal
8
c
to communicate that the bus
9
(
9
a
~
9
h,
9
j
) is able to be used to the erase control part
7
when the command analyzing and status data generating part
6
obtains the request signal
8
b.
The bus
9
(
9
a
~
9
h
) transmits an address signal, a data signal, and a control signal from the command analyzing and status data generating part
6
, the bus
9
i
connects the bus
9
to the erase control part
7
, and the bus
9
j
connects the bus
9
to the write control part
8
. Memory blocks
10
a
~
10
h
are composed of a row decoder, a column decoder, a sense amplifier and a memory array cell. Latch circuits
11
a
~
11
h
temporarily memorize each of an address signal, a data signal and a control signal from the buses
9
a
~
9
h
and transmit these signals to the memory blocks
10
a
~
10
h
. The data once latched are never altered except when they are altered by controlling by the command analyzing and status data generating part
6
. Buses
12
a
~
12
h
connect the latch circuits
11
a
~
11
h.
In
FIG. 8
, buses
14
(
14
a
~
14
h
) are for erasing, and transmit each of an address signal, a data signal and a control signal from the erase control part
7
to the memory blocks
10
a
~
10
h,
and buses
15
(
15
a
~
15
h
) are for writing, and transmit each of an address signal, data signal and control signal from the write control part
8
to the memory blocks
10
a
~
10
h.
Selector circuits
13
a
~
13
h
select one of signals from bus
14
for erasing, bus
15
for writing and bus
9
, to transmit the selected signal to the memory blocks
10
a
~
10
h.
Next, operations will be explained below.
First, a read operation is explained.
When a read signal consisting of a control signal
2
and an address
4
is entered into the command analyzing and status data generating part
6
from the outside, the command analyzing and status data generating part
6
confirms whether a memory block from which data are to be read is busy on an erase operation or a write operation. If the memory block from which data are to be read is busy, then, a status of error is returned to the outside via the data
3
. If the memory block from which data are to be read is not busy, then, a read signal is transmitted through the bus
9
, the latch circuit
11
, and the bus
12
to the memory block
10
to read data from a memory cell in the memory block.
Subsequently, the data to be read are sent from the memory block
10
through the bus
12
, the latch circuit
11
, and the bus
9
to the command analyzing and status data generating part
6
and, then, the read operation is completed when the data which have been read are sent to the outside through the data
3
. Additionally, whether the memory block is busy or not is confirmed by transmitting a read signal to the latch circuits
11
a
~
11
h,
and by thereupon returning a busy signal indicating on operation from the latch circuit
11
to the command analyzing and status data generating part
6
.
Second, a write operation is explained.
When a write signal consisting of the control signal
2
and an address signal
4
, and data to be written and entered through data
3
are entered into the command analyzing and status data generating part
6
from the outside, the command analyzing and status data generating part
6
transmits an operation starting signal to the write control part
8
through the bus
9
j
after having confirmed that the memory block to which data is to be written is not in erasing (on operating) (i.e., after having confirmed that a busy signal indicating on an operation is not returned from the latch circuit
11
, but a read signal indicating on-waiting for a subsequent operation is returned). Then, the write control part
8
makes a status signal
8
b
indicating on a write operation active.
The write control part
8
sends a request for using the bus
9
by a request signal
8
b
to the command analyzing and status data generating part
6
, and when it receives the permission for use of the bus
9
as an acknowledge signal
8
c,
it transmits a write signal and data to be written through the bus
9
, the latch circuit
11
and the bus
12
to the memory block
10
, at this point in time, a write operation starts.
In order to write data, it is needed to keep applying a voltage required to write data to the memory cell for a certain period of time and, this voltage is also applied via the common bus
9
. Therefore, arbitration of using the bus
9
is required. Specifically, since a write operation spends a relatively long time, a read operation is restricted when the write operation is carried out. Consequently, the effect of simultaneous operation is reduced. Therefore, time sharing of the write operation is performed to permit a read operation between the periods of the write operation.
In order to interrupt the write operation once, the state of the bus
9
is saved in the latch circuit
11
and, the operation state of the memory block to which data is written is maintained. After that, the request signal is made to be non-active to open the bus
9
to the command analyzing part and status data
Lebentritt Michael S.
Morrison & Foerster / LLP
Phung Anh
Sharp Kabushiki Kaisha
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