Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-14
2002-05-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185040, C365S024000, C365S185220
Reexamination Certificate
active
06396738
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrically writable and erasable non-volatile semiconductor memory device such as a flash memory or the like.
In recent years, an electrically writable and erasable non-volatile semiconductor memory device (a so-called flash memory) having a plurality of memory cells provided with a floating gate which is an electric load accumulation layer between a gate and a channel is widely used for a data storage of a digital still camera, a digital audio device and a flash card or the like because the cost thereof is low and the device has an electrically erasing function. In such a flash memory, an increase in the capacity is conventionally demanded together with a high-speed rewriting operation. As one of the technique of attempting an increase in the capacity, a multiple-value technique is known. In a binary value flash memory, a threshold value voltage of the memory cell in slow state is set to “1” (or “0”) whereas the threshold value voltage of the memory cell in a high state is set to “0” (or “1”). On the other hand, in the flash memory using the multiple-value technique (hereinafter referred to as a multiple-value flash memory), the flash memory is controlled so that the threshold value voltage of the memory cell is allowed to correspond to the three or more state.
For example, in order to memorize four values, the threshold value voltage of the memory cell is set to four states so that the four states to correspond to “11”, “10”, “00”, and “01”, respectively. Here, let “11” correspond to the lowest state of the threshold value voltage, and “01” correspond to the highest state of the threshold value voltage. As a result, it becomes possible to memorize two bits data in one memory cell.
FIGS. 13 and 14
are views showing one example of a threshold value voltage regulated in accordance with each data added to the memory cell of the multiple-value flash memory. In this example, the threshold value in the lowest state corresponding to “11” is regulated to VF
0
through VFU
0
(for example, 1V through 1.7V), the threshold value voltage in the state corresponding to “10” is regulated to VF
1
through VFU
1
(for example, 2.3V through 2.7V), the threshold value voltage corresponding to “00” is regulated to VF
2
through VFU
2
(for example, 3.3 V through 3.7 V) and the threshold value voltage corresponding to “01” is regulated to VF
3
or more (for example, 4.3V or more).
In this manner, in the multiple-value flash memory, a plurality of threshold value voltages corresponding to each data are regulated in parallel. In such a case, it is necessary to control the threshold value voltage of the memory cell with good precision as compared with the case in which the conventional binary value flash memory is used.
FIG. 15
shows a procedure of a writing operation in the conventional multiple-value flash memory. When the writing operation starts, the data is input (S
51
). After the input of the data, a writing pulse (for example, 18V) is applied to the memory cell in which the state of “01” is to be written (S
52
). Then, the writing verify is conducted at the voltage of VF
3
along with the application of this writing pulse (S
53
). In this writing verify, the data in the memory cell is read by the application of the predetermined verify voltage to, for example, the word line voltage, so that judgment is made as to whether or not the data is normally written by the comparison of this read data with the data to be written. Such a writing pulse application and writing verify are repeated in an interval until judgment is made that the data is normally written. When the verify operation is passed with respect to all the memory cells until the predetermined times are attained (for example, ten times), the process proceeds to the application of the writing pulse of “00” (S
54
). However, the writing pulse is prevented from being applied to the memory cell which has a threshold value voltage of VF
3
or more. On the other hand, in the case where the writing verify is not passed even when the predetermined times are attained, namely, in the case of the presence of the memory cell having the threshold value of not more than VF
3
, time is over and error end is generated.
At steps S
54
& S
55
, and S
56
& S
57
, the writing pulse application and the writing verify are executed in the same manner as the state of “01” described above with respect to the states of “00” and “01”, respectively.
When the application of the writing pulses of “01”, “01”, and “10” and the writing verify are normally completed at steps S
52
through S
57
, the upper sleeve verify operation in the state of “11”, “10” and “01” is subsequently executed (S
58
through S
60
). The upper sleeve verify is an operation of detecting a memory cell whose threshold value voltage becomes too high. When the upper sleeve verify is passed with respect to all the “11”, “10” and “00”, the writing operation is normally completed. On the other hand, for example, in the case where the threshold value voltage of the memory cell which should be in the state of “00” becomes VFU
2
or more, the upper sleeve verify is recognized as “writing failure (hereinafter referred to as a fail)” to judge whether or not the fail is the second time (S
61
). When the fail is the first time, an erasure is executed (S
62
). After the threshold value voltage of the memory cell in the sector is brought back to the state of “11”, the writing operation same as the first time is executed again from S
52
.
Next, an erasure operation in the conventional multiple-value flash memory will be explained by referring to
FIGS. 16 and 17
.
FIG. 16
is a view showing a part of a relation between the threshold value voltage and the verify voltage of the memory cell in the erasure state.
FIG. 17
is a flowchart showing the above erasure operation. The erasure operation in the multiple-value flash memory is the same as the case of the binary-value flash memory. When the erasure operation starts, an erasure pulse, which is a negative high voltage is applied (S
71
). Along with the application of the erasure pulse, an erasure verify is executed to judge whether or not the threshold value voltage of the memory cell becomes a predetermined verify voltage (for example, VER which is 1.6V) or less as shown in
FIG. 16
(S
72
). The erasure pulse application and the erasure verify are repeated in an interval until judgment is made that data erasure is normally executed. When the verify operation is passed with respect to all the memory cells until predetermined times are attained (for example, ten times), the process proceeds to the deplete check (S
73
) On the other hand, in the case where the erasure verify is not passed even if the predetermined times are attained, namely, in the case where the memory cells are present which have the threshold value of VER or less, time is over and error end is generated.
In the deplete check of S
73
, judgment is made as to whether there is any memory cell whose threshold value voltage has become too low (VF
0
). When this deplete check is passed, the erasure operation is normally ended. When judgment is made that the deplete check is NG, the write-back pulse of “11” is applied so that the threshold value voltage of the memory cell becomes VF
0
or more (S
74
) Along with the application of this write-back pulse, the write-back verify is conducted for judging whether or not the threshold value voltage of all the memory cells is VF
0
or more (S
75
). When the write-back verify is passed, the upper sleeve verify of “11” is subsequently executed (S
76
), so that the memory cell which has the threshold voltage of VF
0
or more is detected. In the case where judgment is made that the upper sleeve verify of “11” is OK, the operation is normally ended. On the other hand, in the case where judgment is made that upper sleeve verify is a fail, judgment is made as to whether the fail is the second time or not (S
77
). In the case where the fail is the first time, the erasure operation same as the
Saeki Tatsuya
Tamada Satoru
LandOfFree
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