Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-02-15
2005-02-15
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185210, C365S185110
Reexamination Certificate
active
06856549
ABSTRACT:
A reference cell is connected to two reference bit lines. In data access, when one reference bit line is driven to a selected state in response to a reference column select signal which is a decode result of a column address, a potential of a selected reference bit line is transmitted to a reference data bus line. A potential difference between the reference data bus line and a data bus line is amplified by a sense amplifier, and read data is output from an external terminal. During the access period, a reference bit line in a non-selected state is precharged to a ground potential in response to a reset signal at H level. In the next data access, when the non-selected reference bit line is selected, successive data reading is attained without waiting for a time period for precharging a bit line.
REFERENCES:
patent: 6442070 (2002-08-01), Tanaka et al.
patent: 6487124 (2002-11-01), Semi
patent: 6507525 (2003-01-01), Nobunaga et al.
patent: P2000-100186 (2000-04-01), None
“A 1-Mbit CMOS EPROM with Enhanced Verification”, Roberto Gastaldl et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1150-1156.
Ho Hoai
McDermott Will & Emery LLP
Renesas Technology Corp.
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